100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/*
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* (C) Copyright 2006 DENX Software Engineering
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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/*
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* hardware specific access to control-lines
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* function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
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*/
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static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE )
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MACRO_NAND_CTL_SETCLE((unsigned long)base);
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else
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MACRO_NAND_CTL_CLRCLE((unsigned long)base);
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if ( ctrl & NAND_ALE )
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MACRO_NAND_CTL_CLRCLE((unsigned long)base);
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else
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MACRO_NAND_CTL_CLRALE((unsigned long)base);
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if ( ctrl & NAND_NCE )
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MACRO_NAND_ENABLE_CE((unsigned long)base);
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else
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MACRO_NAND_DISABLE_CE((unsigned long)base);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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/*
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* read device ready pin
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* function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
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*/
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static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong rb_gpio_pin;
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/* use the base addr to find out which chip are we dealing with */
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switch((ulong) this->IO_ADDR_W) {
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case CONFIG_SYS_NAND0_BASE:
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rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
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break;
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case CONFIG_SYS_NAND1_BASE:
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rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
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break;
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default: /* this should never happen */
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return 0;
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break;
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}
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if (in32(GPIO0_IR) & rb_gpio_pin)
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return 1;
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return 0;
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}
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/*
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* Board-specific NAND initialization. The following members of the
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* argument are board-specific (per include/linux/mtd/nand.h):
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* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
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* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
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* - cmd_ctrl: hardwarespecific function for accesing control-lines
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* - dev_ready: hardwarespecific function for accesing device ready/busy line
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* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
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* only be provided if a hardware ECC is available
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* - ecc.mode: mode of ecc, see defines
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* - chip_delay: chip dependent delay for transfering data from array to
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* read regs (tR)
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* - options: various chip options. They can partly be set to inform
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* nand_scan about special functionality. See the defines for further
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* explanation
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* Members with a "?" were not set in the merged testing-NAND branch,
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* so they are not set here either.
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*/
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int board_nand_init(struct nand_chip *nand)
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{
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nand->cmd_ctrl = ppchameleonevb_hwcontrol;
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nand->dev_ready = ppchameleonevb_device_ready;
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->chip_delay = NAND_BIG_DELAY_US;
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nand->options = NAND_SAMSUNG_LP_OPTIONS;
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return 0;
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}
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#endif
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