629 lines
16 KiB
C
629 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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*
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* Rockchip GMAC ethernet IP driver for U-Boot
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*/
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#include <common.h>
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#include <dm.h>
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#include <clk.h>
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#include <phy.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk322x.h>
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#include <asm/arch/grf_rk3288.h>
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#include <asm/arch/grf_rk3328.h>
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#include <asm/arch/grf_rk3368.h>
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#include <asm/arch/grf_rk3399.h>
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#include <asm/arch/grf_rv1108.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include "designware.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DELAY_ENABLE(soc, tx, rx) \
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(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
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((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
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/*
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* Platform data for the gmac
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*
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* dw_eth_pdata: Required platform data for designware driver (must be first)
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*/
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struct gmac_rockchip_platdata {
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struct dw_eth_pdata dw_eth_pdata;
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bool clock_input;
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int tx_delay;
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int rx_delay;
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};
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struct rk_gmac_ops {
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int (*fix_mac_speed)(struct dw_eth_dev *priv);
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void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
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void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
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};
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static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
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{
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struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
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const char *string;
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string = dev_read_string(dev, "clock_in_out");
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if (!strcmp(string, "input"))
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pdata->clock_input = true;
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else
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pdata->clock_input = false;
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/* Check the new naming-style first... */
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pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
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pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
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/* ... and fall back to the old naming style or default, if necessary */
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if (pdata->tx_delay == -ENOENT)
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pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
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if (pdata->rx_delay == -ENOENT)
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pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
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return designware_eth_ofdata_to_platdata(dev);
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}
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static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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{
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struct rk322x_grf *grf;
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int clk;
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enum {
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RK3228_GMAC_CLK_SEL_SHIFT = 8,
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RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
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RK3228_GMAC_CLK_SEL_125M = 0 << 8,
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RK3228_GMAC_CLK_SEL_25M = 3 << 8,
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RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
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};
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switch (priv->phydev->speed) {
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case 10:
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clk = RK3228_GMAC_CLK_SEL_2_5M;
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break;
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case 100:
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clk = RK3228_GMAC_CLK_SEL_25M;
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break;
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case 1000:
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clk = RK3228_GMAC_CLK_SEL_125M;
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break;
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default:
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debug("Unknown phy speed: %d\n", priv->phydev->speed);
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return -EINVAL;
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}
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
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return 0;
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}
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static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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{
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struct rk3288_grf *grf;
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int clk;
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switch (priv->phydev->speed) {
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case 10:
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clk = RK3288_GMAC_CLK_SEL_2_5M;
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break;
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case 100:
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clk = RK3288_GMAC_CLK_SEL_25M;
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break;
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case 1000:
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clk = RK3288_GMAC_CLK_SEL_125M;
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break;
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default:
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debug("Unknown phy speed: %d\n", priv->phydev->speed);
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return -EINVAL;
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}
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
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return 0;
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}
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static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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{
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struct rk3328_grf_regs *grf;
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int clk;
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enum {
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RK3328_GMAC_CLK_SEL_SHIFT = 11,
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RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
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RK3328_GMAC_CLK_SEL_125M = 0 << 11,
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RK3328_GMAC_CLK_SEL_25M = 3 << 11,
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RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
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};
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switch (priv->phydev->speed) {
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case 10:
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clk = RK3328_GMAC_CLK_SEL_2_5M;
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break;
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case 100:
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clk = RK3328_GMAC_CLK_SEL_25M;
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break;
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case 1000:
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clk = RK3328_GMAC_CLK_SEL_125M;
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break;
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default:
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debug("Unknown phy speed: %d\n", priv->phydev->speed);
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return -EINVAL;
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}
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
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return 0;
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}
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static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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{
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struct rk3368_grf *grf;
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int clk;
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enum {
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RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
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RK3368_GMAC_CLK_SEL_25M = 3 << 4,
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RK3368_GMAC_CLK_SEL_125M = 0 << 4,
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RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
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};
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switch (priv->phydev->speed) {
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case 10:
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clk = RK3368_GMAC_CLK_SEL_2_5M;
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break;
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case 100:
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clk = RK3368_GMAC_CLK_SEL_25M;
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break;
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case 1000:
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clk = RK3368_GMAC_CLK_SEL_125M;
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break;
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default:
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debug("Unknown phy speed: %d\n", priv->phydev->speed);
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return -EINVAL;
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}
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
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return 0;
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}
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static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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{
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struct rk3399_grf_regs *grf;
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int clk;
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switch (priv->phydev->speed) {
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case 10:
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clk = RK3399_GMAC_CLK_SEL_2_5M;
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break;
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case 100:
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clk = RK3399_GMAC_CLK_SEL_25M;
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break;
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case 1000:
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clk = RK3399_GMAC_CLK_SEL_125M;
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break;
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default:
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debug("Unknown phy speed: %d\n", priv->phydev->speed);
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return -EINVAL;
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}
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
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return 0;
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}
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static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
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{
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struct rv1108_grf *grf;
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int clk, speed;
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enum {
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RV1108_GMAC_SPEED_MASK = BIT(2),
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RV1108_GMAC_SPEED_10M = 0 << 2,
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RV1108_GMAC_SPEED_100M = 1 << 2,
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RV1108_GMAC_CLK_SEL_MASK = BIT(7),
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RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
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RV1108_GMAC_CLK_SEL_25M = 1 << 7,
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};
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switch (priv->phydev->speed) {
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case 10:
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clk = RV1108_GMAC_CLK_SEL_2_5M;
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speed = RV1108_GMAC_SPEED_10M;
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break;
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case 100:
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clk = RV1108_GMAC_CLK_SEL_25M;
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speed = RV1108_GMAC_SPEED_100M;
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break;
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default:
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debug("Unknown phy speed: %d\n", priv->phydev->speed);
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return -EINVAL;
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}
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->gmac_con0,
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RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
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clk | speed);
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return 0;
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}
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static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
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{
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struct rk322x_grf *grf;
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enum {
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RK3228_RMII_MODE_SHIFT = 10,
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RK3228_RMII_MODE_MASK = BIT(10),
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RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
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RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
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RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
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RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
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RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
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RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
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RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
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RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
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RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
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};
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enum {
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RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
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RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
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RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
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RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
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};
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->mac_con[1],
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RK3228_RMII_MODE_MASK |
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RK3228_GMAC_PHY_INTF_SEL_MASK |
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RK3228_RXCLK_DLY_ENA_GMAC_MASK |
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RK3228_TXCLK_DLY_ENA_GMAC_MASK,
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RK3228_GMAC_PHY_INTF_SEL_RGMII |
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DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
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rk_clrsetreg(&grf->mac_con[0],
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RK3228_CLK_RX_DL_CFG_GMAC_MASK |
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RK3228_CLK_TX_DL_CFG_GMAC_MASK,
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pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
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pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
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}
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static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
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{
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struct rk3288_grf *grf;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con1,
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RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
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RK3288_GMAC_PHY_INTF_SEL_RGMII);
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rk_clrsetreg(&grf->soc_con3,
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RK3288_RXCLK_DLY_ENA_GMAC_MASK |
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RK3288_TXCLK_DLY_ENA_GMAC_MASK |
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RK3288_CLK_RX_DL_CFG_GMAC_MASK |
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RK3288_CLK_TX_DL_CFG_GMAC_MASK,
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DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
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pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
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pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
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}
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static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
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{
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struct rk3328_grf_regs *grf;
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enum {
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RK3328_RMII_MODE_SHIFT = 9,
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RK3328_RMII_MODE_MASK = BIT(9),
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RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
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RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
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RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
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RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
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RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
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RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
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RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
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RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
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RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
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};
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enum {
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RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
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RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
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RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
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RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
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};
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->mac_con[1],
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RK3328_RMII_MODE_MASK |
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RK3328_GMAC_PHY_INTF_SEL_MASK |
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RK3328_RXCLK_DLY_ENA_GMAC_MASK |
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RK3328_TXCLK_DLY_ENA_GMAC_MASK,
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RK3328_GMAC_PHY_INTF_SEL_RGMII |
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DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
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rk_clrsetreg(&grf->mac_con[0],
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RK3328_CLK_RX_DL_CFG_GMAC_MASK |
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RK3328_CLK_TX_DL_CFG_GMAC_MASK,
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pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
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pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
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}
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static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
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{
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struct rk3368_grf *grf;
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enum {
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RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
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RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
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RK3368_RMII_MODE_MASK = BIT(6),
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RK3368_RMII_MODE = BIT(6),
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};
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enum {
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RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
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RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
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RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
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RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
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RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
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RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
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RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
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RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
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RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
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RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
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};
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con15,
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RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
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RK3368_GMAC_PHY_INTF_SEL_RGMII);
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rk_clrsetreg(&grf->soc_con16,
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RK3368_RXCLK_DLY_ENA_GMAC_MASK |
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RK3368_TXCLK_DLY_ENA_GMAC_MASK |
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RK3368_CLK_RX_DL_CFG_GMAC_MASK |
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RK3368_CLK_TX_DL_CFG_GMAC_MASK,
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DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
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pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
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pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
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}
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static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
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{
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struct rk3399_grf_regs *grf;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con5,
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RK3399_GMAC_PHY_INTF_SEL_MASK,
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RK3399_GMAC_PHY_INTF_SEL_RGMII);
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rk_clrsetreg(&grf->soc_con6,
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RK3399_RXCLK_DLY_ENA_GMAC_MASK |
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RK3399_TXCLK_DLY_ENA_GMAC_MASK |
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RK3399_CLK_RX_DL_CFG_GMAC_MASK |
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RK3399_CLK_TX_DL_CFG_GMAC_MASK,
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DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
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pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
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pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
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}
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static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
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{
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struct rv1108_grf *grf;
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enum {
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RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
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RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
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};
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
rk_clrsetreg(&grf->gmac_con0,
|
|
RV1108_GMAC_PHY_INTF_SEL_MASK,
|
|
RV1108_GMAC_PHY_INTF_SEL_RMII);
|
|
}
|
|
|
|
static int gmac_rockchip_probe(struct udevice *dev)
|
|
{
|
|
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
|
|
struct rk_gmac_ops *ops =
|
|
(struct rk_gmac_ops *)dev_get_driver_data(dev);
|
|
struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
|
|
struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
|
|
struct clk clk;
|
|
ulong rate;
|
|
int ret;
|
|
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
switch (eth_pdata->phy_interface) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
/* Set to RGMII mode */
|
|
if (ops->set_to_rgmii)
|
|
ops->set_to_rgmii(pdata);
|
|
else
|
|
return -EPERM;
|
|
|
|
/*
|
|
* If the gmac clock is from internal pll, need to set and
|
|
* check the return value for gmac clock at RGMII mode. If
|
|
* the gmac clock is from external source, the clock rate
|
|
* is not set, because of it is bypassed.
|
|
*/
|
|
|
|
if (!pdata->clock_input) {
|
|
rate = clk_set_rate(&clk, 125000000);
|
|
if (rate != 125000000)
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
/* Set to RGMII mode */
|
|
if (ops->set_to_rgmii) {
|
|
pdata->tx_delay = 0;
|
|
pdata->rx_delay = 0;
|
|
ops->set_to_rgmii(pdata);
|
|
} else
|
|
return -EPERM;
|
|
|
|
if (!pdata->clock_input) {
|
|
rate = clk_set_rate(&clk, 125000000);
|
|
if (rate != 125000000)
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
/* Set to RMII mode */
|
|
if (ops->set_to_rmii)
|
|
ops->set_to_rmii(pdata);
|
|
else
|
|
return -EPERM;
|
|
|
|
if (!pdata->clock_input) {
|
|
rate = clk_set_rate(&clk, 50000000);
|
|
if (rate != 50000000)
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
/* Set to RGMII_RXID mode */
|
|
if (ops->set_to_rgmii) {
|
|
pdata->tx_delay = 0;
|
|
ops->set_to_rgmii(pdata);
|
|
} else
|
|
return -EPERM;
|
|
|
|
if (!pdata->clock_input) {
|
|
rate = clk_set_rate(&clk, 125000000);
|
|
if (rate != 125000000)
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
/* Set to RGMII_TXID mode */
|
|
if (ops->set_to_rgmii) {
|
|
pdata->rx_delay = 0;
|
|
ops->set_to_rgmii(pdata);
|
|
} else
|
|
return -EPERM;
|
|
|
|
if (!pdata->clock_input) {
|
|
rate = clk_set_rate(&clk, 125000000);
|
|
if (rate != 125000000)
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
debug("NO interface defined!\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
return designware_eth_probe(dev);
|
|
}
|
|
|
|
static int gmac_rockchip_eth_start(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
struct rk_gmac_ops *ops =
|
|
(struct rk_gmac_ops *)dev_get_driver_data(dev);
|
|
int ret;
|
|
|
|
ret = designware_eth_init(priv, pdata->enetaddr);
|
|
if (ret)
|
|
return ret;
|
|
ret = ops->fix_mac_speed(priv);
|
|
if (ret)
|
|
return ret;
|
|
ret = designware_eth_enable(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct eth_ops gmac_rockchip_eth_ops = {
|
|
.start = gmac_rockchip_eth_start,
|
|
.send = designware_eth_send,
|
|
.recv = designware_eth_recv,
|
|
.free_pkt = designware_eth_free_pkt,
|
|
.stop = designware_eth_stop,
|
|
.write_hwaddr = designware_eth_write_hwaddr,
|
|
};
|
|
|
|
const struct rk_gmac_ops rk3228_gmac_ops = {
|
|
.fix_mac_speed = rk3228_gmac_fix_mac_speed,
|
|
.set_to_rgmii = rk3228_gmac_set_to_rgmii,
|
|
};
|
|
|
|
const struct rk_gmac_ops rk3288_gmac_ops = {
|
|
.fix_mac_speed = rk3288_gmac_fix_mac_speed,
|
|
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
|
|
};
|
|
|
|
const struct rk_gmac_ops rk3328_gmac_ops = {
|
|
.fix_mac_speed = rk3328_gmac_fix_mac_speed,
|
|
.set_to_rgmii = rk3328_gmac_set_to_rgmii,
|
|
};
|
|
|
|
const struct rk_gmac_ops rk3368_gmac_ops = {
|
|
.fix_mac_speed = rk3368_gmac_fix_mac_speed,
|
|
.set_to_rgmii = rk3368_gmac_set_to_rgmii,
|
|
};
|
|
|
|
const struct rk_gmac_ops rk3399_gmac_ops = {
|
|
.fix_mac_speed = rk3399_gmac_fix_mac_speed,
|
|
.set_to_rgmii = rk3399_gmac_set_to_rgmii,
|
|
};
|
|
|
|
const struct rk_gmac_ops rv1108_gmac_ops = {
|
|
.fix_mac_speed = rv1108_set_rmii_speed,
|
|
.set_to_rmii = rv1108_gmac_set_to_rmii,
|
|
};
|
|
|
|
static const struct udevice_id rockchip_gmac_ids[] = {
|
|
{ .compatible = "rockchip,rk3228-gmac",
|
|
.data = (ulong)&rk3228_gmac_ops },
|
|
{ .compatible = "rockchip,rk3288-gmac",
|
|
.data = (ulong)&rk3288_gmac_ops },
|
|
{ .compatible = "rockchip,rk3328-gmac",
|
|
.data = (ulong)&rk3328_gmac_ops },
|
|
{ .compatible = "rockchip,rk3368-gmac",
|
|
.data = (ulong)&rk3368_gmac_ops },
|
|
{ .compatible = "rockchip,rk3399-gmac",
|
|
.data = (ulong)&rk3399_gmac_ops },
|
|
{ .compatible = "rockchip,rv1108-gmac",
|
|
.data = (ulong)&rv1108_gmac_ops },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_gmac_rockchip) = {
|
|
.name = "gmac_rockchip",
|
|
.id = UCLASS_ETH,
|
|
.of_match = rockchip_gmac_ids,
|
|
.ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
|
|
.probe = gmac_rockchip_probe,
|
|
.ops = &gmac_rockchip_eth_ops,
|
|
.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
|
|
.platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|