72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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/* CPU specific code */
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#include <common.h>
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#include <cpu_func.h>
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#include <irq_func.h>
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#include <asm/cache.h>
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#include <asm/csr.h>
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MMISC_CTL 0x7d0
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#define CSR_MARCHID 0xf12
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#define V5_MCACHE_CTL_IC_EN_OFFSET 0
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#define V5_MCACHE_CTL_DC_EN_OFFSET 1
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#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
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#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
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#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
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#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
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#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
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#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
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/*
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* cleanup_before_linux() is called just before we call linux
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* it prepares the processor for linux
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*
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* we disable interrupt and caches.
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*/
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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/* turn off I/D-cache */
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cache_flush();
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icache_disable();
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dcache_disable();
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return 0;
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}
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void harts_early_init(void)
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{
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if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
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unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
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if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
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mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
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if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
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mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
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if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
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mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
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csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
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/*
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* Check DC_COHEN_EN, if cannot write to mcache_ctl,
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* we assume this bitmap not support L2 CM
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*/
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mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
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if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
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/* Wait for DC_COHSTA bit be set */
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while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
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mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
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}
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}
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}
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