586 lines
12 KiB
C
586 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#include <common.h>
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#include <command.h>
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#include <console.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <gdsys_fpga.h>
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#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
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#include <dm.h>
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#include <misc.h>
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#include <regmap.h>
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#include <sysinfo.h>
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#include "../../../drivers/misc/gdsys_soc.h"
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#include "../../../drivers/misc/gdsys_ioep.h"
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#include "../../../drivers/misc/ihs_fpga.h"
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const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
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#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
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enum status_print_type {
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STATUS_LOUD = 0,
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STATUS_SILENT = 1,
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};
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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enum {
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STATE_TX_PACKET_BUILDING = BIT(0),
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STATE_TX_TRANSMITTING = BIT(1),
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STATE_TX_BUFFER_FULL = BIT(2),
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STATE_TX_ERR = BIT(3),
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STATE_RECEIVE_TIMEOUT = BIT(4),
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STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
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STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
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STATE_RX_DIST_ERR = BIT(7),
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STATE_RX_LENGTH_ERR = BIT(8),
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STATE_RX_FRAME_CTR_ERR = BIT(9),
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STATE_RX_FCS_ERR = BIT(10),
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STATE_RX_PACKET_DROPPED = BIT(11),
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STATE_RX_DATA_LAST = BIT(12),
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STATE_RX_DATA_FIRST = BIT(13),
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STATE_RX_DATA_AVAILABLE = BIT(15),
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};
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enum {
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IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
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IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
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IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
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IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
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};
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enum {
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CTRL_PROC_RECEIVE_ENABLE = BIT(12),
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CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
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};
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struct io_generic_packet {
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u16 target_address;
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u16 source_address;
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u8 packet_type;
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u8 bc;
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u16 packet_length;
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} __attribute__((__packed__));
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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unsigned long long rx_ctr;
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unsigned long long tx_ctr;
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unsigned long long err_ctr;
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#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
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struct udevice *dev;
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#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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static void io_check_status(uint fpga, u16 status, enum status_print_type type)
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{
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u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
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STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
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STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
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if (!(status & mask)) {
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FPGA_SET_REG(fpga, ep.rx_tx_status, status);
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return;
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}
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err_ctr++;
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FPGA_SET_REG(fpga, ep.rx_tx_status, status);
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if (type == STATUS_SILENT)
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return;
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if (status & STATE_RX_PACKET_DROPPED)
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printf("RX_PACKET_DROPPED, status %04x\n", status);
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if (status & STATE_RX_DIST_ERR)
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printf("RX_DIST_ERR\n");
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if (status & STATE_RX_LENGTH_ERR)
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printf("RX_LENGTH_ERR\n");
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if (status & STATE_RX_FRAME_CTR_ERR)
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printf("RX_FRAME_CTR_ERR\n");
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if (status & STATE_RX_FCS_ERR)
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printf("RX_FCS_ERR\n");
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if (status & STATE_TX_ERR)
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printf("TX_ERR\n");
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}
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#else
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static void io_check_status(struct udevice *dev, enum status_print_type type)
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{
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u16 status = 0;
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int ret;
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ret = misc_call(dev, 0, NULL, 0, &status, 0);
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if (!ret)
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return;
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err_ctr++;
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if (type != STATUS_LOUD)
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return;
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if (status & STATE_RX_PACKET_DROPPED)
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printf("RX_PACKET_DROPPED, status %04x\n", status);
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if (status & STATE_RX_DIST_ERR)
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printf("RX_DIST_ERR\n");
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if (status & STATE_RX_LENGTH_ERR)
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printf("RX_LENGTH_ERR\n");
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if (status & STATE_RX_FRAME_CTR_ERR)
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printf("RX_FRAME_CTR_ERR\n");
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if (status & STATE_RX_FCS_ERR)
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printf("RX_FCS_ERR\n");
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if (status & STATE_TX_ERR)
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printf("TX_ERR\n");
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}
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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static void io_send(uint fpga, uint size)
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{
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uint k;
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struct io_generic_packet packet = {
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.source_address = 1,
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.packet_type = 1,
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.packet_length = size,
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};
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u16 *p = (u16 *)&packet;
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for (k = 0; k < sizeof(packet) / 2; ++k)
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FPGA_SET_REG(fpga, ep.transmit_data, *p++);
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for (k = 0; k < (size + 1) / 2; ++k)
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FPGA_SET_REG(fpga, ep.transmit_data, k);
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FPGA_SET_REG(fpga, ep.rx_tx_control,
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CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
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tx_ctr++;
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}
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#else
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static void io_send(struct udevice *dev, uint size)
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{
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uint k;
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u16 buffer[HEADER_WORDS + 128];
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struct io_generic_packet header = {
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.source_address = 1,
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.packet_type = 1,
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.packet_length = size,
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};
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const uint words = (size + 1) / 2;
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memcpy(buffer, &header, 2 * HEADER_WORDS);
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for (k = 0; k < words; ++k)
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buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);
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misc_write(dev, 0, buffer, HEADER_WORDS + words);
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tx_ctr++;
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}
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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static void io_receive(uint fpga)
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{
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
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u16 rx;
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if (rx_tx_status & STATE_RX_DATA_LAST)
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rx_ctr++;
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FPGA_GET_REG(fpga, ep.receive_data, &rx);
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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}
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}
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#else
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static void io_receive(struct udevice *dev)
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{
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u16 buffer[HEADER_WORDS + 128];
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if (!misc_read(dev, 0, buffer, 0))
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rx_ctr++;
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}
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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static void io_reflect(uint fpga)
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{
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u16 buffer[128];
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uint k = 0;
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uint n;
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
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FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
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if (rx_tx_status & STATE_RX_DATA_LAST)
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break;
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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}
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if (!k)
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return;
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for (n = 0; n < k; ++n)
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FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
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FPGA_SET_REG(fpga, ep.rx_tx_control,
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CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
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tx_ctr++;
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}
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#else
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static void io_reflect(struct udevice *dev)
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{
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u16 buffer[HEADER_WORDS + 128];
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struct io_generic_packet *header;
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if (misc_read(dev, 0, buffer, 0))
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return;
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header = (struct io_generic_packet *)&buffer;
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misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
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}
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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/*
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* FPGA io-endpoint reflector
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*
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* Syntax:
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* ioreflect {fpga} {reportrate}
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*/
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int do_ioreflect(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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uint fpga;
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uint rate = 0;
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unsigned long long last_seen = 0;
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if (argc < 2)
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return CMD_RET_USAGE;
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fpga = dectoul(argv[1], NULL);
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/*
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* If another parameter, it is the report rate in packets.
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*/
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if (argc > 2)
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rate = dectoul(argv[2], NULL);
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/* Enable receive path */
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FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
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/* Set device address to dummy 1*/
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FPGA_SET_REG(fpga, ep.device_address, 1);
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
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while (1) {
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u16 top_int;
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, top_interrupt, &top_int);
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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io_check_status(fpga, rx_tx_status, STATUS_SILENT);
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if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
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(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
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io_reflect(fpga);
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if (rate) {
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if (!(tx_ctr % rate) && (tx_ctr != last_seen))
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printf("refl %llu, err %llu\n", tx_ctr,
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err_ctr);
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last_seen = tx_ctr;
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}
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if (ctrlc())
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break;
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}
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return 0;
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}
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#else
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/*
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* FPGA io-endpoint reflector
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*
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* Syntax:
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* ioreflect {reportrate}
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*/
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int do_ioreflect(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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struct udevice *fpga;
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struct regmap *map;
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uint rate = 0;
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unsigned long long last_seen = 0;
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if (!dev) {
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printf("No device selected\n");
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return 1;
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}
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gdsys_soc_get_fpga(dev, &fpga);
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regmap_init_mem(dev_ofnode(dev), &map);
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/* Enable receive path */
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misc_set_enabled(dev, true);
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
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while (1) {
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uint top_int;
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ihs_fpga_get(map, top_interrupt, &top_int);
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io_check_status(dev, STATUS_SILENT);
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if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
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(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
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io_reflect(dev);
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if (rate) {
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if (!(tx_ctr % rate) && (tx_ctr != last_seen))
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printf("refl %llu, err %llu\n", tx_ctr,
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err_ctr);
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last_seen = tx_ctr;
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}
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if (ctrlc())
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break;
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}
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return 0;
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}
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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#define DISP_LINE_LEN 16
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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/*
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* FPGA io-endpoint looptest
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*
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* Syntax:
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* ioloop {fpga} {size} {rate}
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*/
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int do_ioloop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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uint fpga;
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uint size;
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uint rate = 0;
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if (argc < 3)
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return CMD_RET_USAGE;
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/*
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* FPGA is specified since argc > 2
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*/
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fpga = dectoul(argv[1], NULL);
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/*
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* packet size is specified since argc > 2
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*/
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size = dectoul(argv[2], NULL);
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/*
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* If another parameter, it is the test rate in packets per second.
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*/
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if (argc > 3)
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rate = dectoul(argv[3], NULL);
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/* enable receive path */
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FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
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/* set device address to dummy 1*/
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FPGA_SET_REG(fpga, ep.device_address, 1);
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
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while (1) {
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u16 top_int;
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, top_interrupt, &top_int);
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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io_check_status(fpga, rx_tx_status, STATUS_LOUD);
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if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
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io_send(fpga, size);
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if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
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io_receive(fpga);
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if (rate) {
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if (ctrlc())
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break;
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udelay(1000000 / rate);
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if (!(tx_ctr % rate))
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printf("d %llu, tx %llu, rx %llu, err %llu\n",
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tx_ctr - rx_ctr, tx_ctr, rx_ctr,
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err_ctr);
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}
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}
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return 0;
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}
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#else
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/*
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* FPGA io-endpoint looptest
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*
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* Syntax:
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* ioloop {size} {rate}
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*/
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int do_ioloop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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uint size;
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uint rate = 0;
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struct udevice *fpga;
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struct regmap *map;
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if (!dev) {
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printf("No device selected\n");
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return 1;
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}
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gdsys_soc_get_fpga(dev, &fpga);
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regmap_init_mem(dev_ofnode(dev), &map);
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if (argc < 2)
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return CMD_RET_USAGE;
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/*
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* packet size is specified since argc > 1
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*/
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size = dectoul(argv[2], NULL);
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/*
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* If another parameter, it is the test rate in packets per second.
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*/
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if (argc > 2)
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rate = dectoul(argv[3], NULL);
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/* Enable receive path */
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misc_set_enabled(dev, true);
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
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while (1) {
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uint top_int;
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if (ctrlc())
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break;
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ihs_fpga_get(map, top_interrupt, &top_int);
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io_check_status(dev, STATUS_LOUD);
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if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
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io_send(dev, size);
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if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
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io_receive(dev);
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if (rate) {
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udelay(1000000 / rate);
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if (!(tx_ctr % rate))
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printf("d %llu, tx %llu, rx %llu, err %llu\n",
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tx_ctr - rx_ctr, tx_ctr, rx_ctr,
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err_ctr);
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}
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}
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return 0;
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}
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
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int do_iodev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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struct udevice *ioep = NULL;
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struct udevice *sysinfo;
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char name[8];
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int ret;
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if (sysinfo_get(&sysinfo))
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return CMD_RET_FAILURE;
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if (argc > 1) {
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int i = dectoul(argv[1], NULL);
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snprintf(name, sizeof(name), "ioep%d", i);
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ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, name,
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&ioep);
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if (ret || !ioep) {
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printf("Invalid IOEP %d\n", i);
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return CMD_RET_FAILURE;
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}
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dev = ioep;
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} else {
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int i = 0;
|
|
|
|
while (1) {
|
|
snprintf(name, sizeof(name), "ioep%d", i);
|
|
|
|
ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo,
|
|
name, &ioep);
|
|
|
|
if (ret || !ioep)
|
|
break;
|
|
|
|
printf("IOEP %d:\t%s\n", i++, ioep->name);
|
|
}
|
|
|
|
if (dev)
|
|
printf("\nSelected IOEP: %s\n", dev->name);
|
|
else
|
|
puts("\nNo IOEP selected.\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
|
|
|
|
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
|
U_BOOT_CMD(
|
|
ioloop, 4, 0, do_ioloop,
|
|
"fpga io-endpoint looptest",
|
|
"fpga packetsize [packets/sec]"
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
ioreflect, 3, 0, do_ioreflect,
|
|
"fpga io-endpoint reflector",
|
|
"fpga reportrate"
|
|
);
|
|
#else
|
|
U_BOOT_CMD(
|
|
ioloop, 3, 0, do_ioloop,
|
|
"fpga io-endpoint looptest",
|
|
"packetsize [packets/sec]"
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
ioreflect, 2, 0, do_ioreflect,
|
|
"fpga io-endpoint reflector",
|
|
"reportrate"
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
iodev, 2, 0, do_iodev,
|
|
"fpga io-endpoint listing/selection",
|
|
"[ioep device to select]"
|
|
);
|
|
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|