160 lines
3.3 KiB
C
160 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dt-bindings/clock/mt7620-clk.h>
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#include <misc.h>
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#include <mach/mt7620-sysc.h>
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/* CLKCFG1 */
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#define CLKCFG1_REG 0x30
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#define CLK_SRC_CPU -1
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#define CLK_SRC_CPU_D2 -2
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#define CLK_SRC_SYS -3
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#define CLK_SRC_XTAL -4
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#define CLK_SRC_PERI -5
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struct mt7620_clk_priv {
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struct udevice *dev;
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struct udevice *sysc;
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struct mt7620_sysc_clks clks;
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};
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static const int mt7620_clks[] = {
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[CLK_SYS] = CLK_SRC_SYS,
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[CLK_CPU] = CLK_SRC_CPU,
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[CLK_XTAL] = CLK_SRC_XTAL,
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[CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
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[CLK_UARTF] = CLK_SRC_PERI,
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[CLK_UARTL] = CLK_SRC_PERI,
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[CLK_SPI] = CLK_SRC_SYS,
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[CLK_I2C] = CLK_SRC_PERI,
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[CLK_I2S] = CLK_SRC_PERI,
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};
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static ulong mt7620_clk_get_rate(struct clk *clk)
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{
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struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id >= ARRAY_SIZE(mt7620_clks))
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return 0;
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switch (mt7620_clks[clk->id]) {
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case CLK_SRC_CPU:
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return priv->clks.cpu_clk;
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case CLK_SRC_CPU_D2:
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return priv->clks.cpu_clk / 2;
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case CLK_SRC_SYS:
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return priv->clks.sys_clk;
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case CLK_SRC_XTAL:
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return priv->clks.xtal_clk;
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case CLK_SRC_PERI:
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return priv->clks.peri_clk;
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default:
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return mt7620_clks[clk->id];
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}
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}
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static int mt7620_clkcfg1_rmw(struct mt7620_clk_priv *priv, u32 clr, u32 set)
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{
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u32 val;
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int ret;
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ret = misc_read(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
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if (ret) {
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dev_err(priv->dev, "mt7620_clk: failed to read CLKCFG1\n");
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return ret;
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}
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val &= ~clr;
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val |= set;
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ret = misc_write(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
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if (ret) {
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dev_err(priv->dev, "mt7620_clk: failed to write CLKCFG1\n");
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return ret;
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}
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return 0;
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}
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static int mt7620_clk_enable(struct clk *clk)
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{
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struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id > 30)
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return -1;
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return mt7620_clkcfg1_rmw(priv, 0, BIT(clk->id));
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}
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static int mt7620_clk_disable(struct clk *clk)
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{
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struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id > 30)
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return -1;
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return mt7620_clkcfg1_rmw(priv, BIT(clk->id), 0);
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}
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const struct clk_ops mt7620_clk_ops = {
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.enable = mt7620_clk_enable,
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.disable = mt7620_clk_disable,
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.get_rate = mt7620_clk_get_rate,
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};
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static int mt7620_clk_probe(struct udevice *dev)
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{
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struct mt7620_clk_priv *priv = dev_get_priv(dev);
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struct ofnode_phandle_args sysc_args;
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int ret;
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ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "mediatek,sysc", NULL,
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0, 0, &sysc_args);
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if (ret) {
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dev_err(dev, "mt7620_clk: sysc property not found\n");
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return ret;
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}
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ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node,
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&priv->sysc);
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if (ret) {
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dev_err(dev, "mt7620_clk: failed to sysc device\n");
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return ret;
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}
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ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CLK,
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&priv->clks);
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if (ret) {
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dev_err(dev, "mt7620_clk: failed to get base clocks\n");
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return ret;
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}
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priv->dev = dev;
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return 0;
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}
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static const struct udevice_id mt7620_clk_ids[] = {
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{ .compatible = "mediatek,mt7620-clk" },
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{ }
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};
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U_BOOT_DRIVER(mt7620_clk) = {
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.name = "mt7620-clk",
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.id = UCLASS_CLK,
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.of_match = mt7620_clk_ids,
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.probe = mt7620_clk_probe,
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.priv_auto = sizeof(struct mt7620_clk_priv),
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.ops = &mt7620_clk_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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