159 lines
4.6 KiB
C
159 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2021 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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* Zong Li
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* Pragnesh Patel
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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#include "sifive-prci.h"
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#include <asm/io.h>
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int sifive_prci_fu740_pcieauxclk_enable(struct __prci_clock *pc, bool enable)
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{
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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u32 v;
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if (pwd->cfg1_offs != PRCI_PCIEAUXCFG1_OFFSET)
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return -EINVAL;
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v = readl(pd->va + pwd->cfg1_offs);
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v = enable ? (v | PRCI_PCIEAUXCFG1_MASK) : (v & ~PRCI_PCIEAUXCFG1_MASK);
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writel(v, pd->va + pwd->cfg1_offs);
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return 0;
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}
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/* PRCI integration data for each WRPLL instance */
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static struct __prci_wrpll_data __prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
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};
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static struct __prci_wrpll_data __prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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.release_reset = sifive_prci_ddr_release_reset,
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};
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static struct __prci_wrpll_data __prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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.release_reset = sifive_prci_ethernet_release_reset,
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};
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static struct __prci_wrpll_data __prci_dvfscorepll_data = {
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.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_corepllsel_use_corepll,
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.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
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};
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static struct __prci_wrpll_data __prci_hfpclkpll_data = {
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.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
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.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
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};
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static struct __prci_wrpll_data __prci_cltxpll_data = {
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.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
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.release_reset = sifive_prci_cltx_release_reset,
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};
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static struct __prci_wrpll_data __prci_pcieaux_data = {
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.cfg1_offs = PRCI_PCIEAUXCFG1_OFFSET,
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};
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/* Linux clock framework integration */
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static const struct __prci_clock_ops sifive_fu740_prci_wrpll_clk_ops = {
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.set_rate = sifive_prci_wrpll_set_rate,
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.round_rate = sifive_prci_wrpll_round_rate,
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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.enable_clk = sifive_prci_clock_enable,
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};
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static const struct __prci_clock_ops sifive_fu740_prci_tlclksel_clk_ops = {
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.recalc_rate = sifive_prci_tlclksel_recalc_rate,
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};
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static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
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.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
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};
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static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
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.enable_clk = sifive_prci_fu740_pcieauxclk_enable,
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};
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/* List of clock controls provided by the PRCI */
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struct __prci_clock __prci_init_clocks_fu740[] = {
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[FU740_PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_corepll_data,
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},
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[FU740_PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_ddrpll_data,
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},
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[FU740_PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_gemgxlpll_data,
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},
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[FU740_PRCI_CLK_DVFSCOREPLL] = {
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.name = "dvfscorepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_dvfscorepll_data,
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},
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[FU740_PRCI_CLK_HFPCLKPLL] = {
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.name = "hfpclkpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_hfpclkpll_data,
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},
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[FU740_PRCI_CLK_CLTXPLL] = {
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.name = "cltxpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_cltxpll_data,
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},
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[FU740_PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu740_prci_tlclksel_clk_ops,
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},
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[FU740_PRCI_CLK_PCLK] = {
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.name = "pclk",
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.parent_name = "hfpclkpll",
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.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
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},
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[FU740_PRCI_CLK_PCIE_AUX] {
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.name = "pcieaux",
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.parent_name = "",
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.ops = &sifive_fu740_prci_pcieaux_clk_ops,
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.pwd = &__prci_pcieaux_data,
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}
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};
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