417 lines
11 KiB
C
417 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020,2021 NXP
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* Layerscape PCIe driver
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <pci.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <malloc.h>
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#include <dm.h>
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#include <dm/devres.h>
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#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
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defined(CONFIG_ARM)
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#include <asm/arch/clock.h>
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#endif
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#include "pcie_layerscape.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct ls_pcie_drvdata {
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u32 lut_offset;
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u32 ctrl_offset;
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bool big_endian;
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};
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static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_cfg1_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
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{
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struct pci_region *io, *mem, *pref;
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unsigned long long offset = 0;
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struct ls_pcie *pcie = pcie_rc->pcie;
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int idx = 0;
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uint svr;
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svr = get_svr();
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if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
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offset = LS1021_PCIE_SPACE_OFFSET +
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LS1021_PCIE_SPACE_SIZE * pcie->idx;
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}
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/* ATU 0 : OUTBOUND : CFG0 */
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ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_CFG0,
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pcie_rc->cfg_res.start + offset,
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0,
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fdt_resource_size(&pcie_rc->cfg_res) / 2);
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/* ATU 1 : OUTBOUND : CFG1 */
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ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_CFG1,
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pcie_rc->cfg_res.start + offset +
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fdt_resource_size(&pcie_rc->cfg_res) / 2,
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0,
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fdt_resource_size(&pcie_rc->cfg_res) / 2);
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pci_get_regions(pcie_rc->bus, &io, &mem, &pref);
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idx = PCIE_ATU_REGION_INDEX1 + 1;
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/* Fix the pcie memory map for LS2088A series SoCs */
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svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A) {
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if (io)
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io->phys_start = (io->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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if (mem)
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mem->phys_start = (mem->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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if (pref)
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pref->phys_start = (pref->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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}
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if (io)
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/* ATU : OUTBOUND : IO */
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ls_pcie_atu_outbound_set(pcie, idx++,
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PCIE_ATU_TYPE_IO,
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io->phys_start + offset,
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io->bus_start,
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io->size);
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if (mem)
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/* ATU : OUTBOUND : MEM */
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ls_pcie_atu_outbound_set(pcie, idx++,
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PCIE_ATU_TYPE_MEM,
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mem->phys_start + offset,
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mem->bus_start,
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mem->size);
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if (pref)
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/* ATU : OUTBOUND : pref */
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ls_pcie_atu_outbound_set(pcie, idx++,
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PCIE_ATU_TYPE_MEM,
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pref->phys_start + offset,
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pref->bus_start,
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pref->size);
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ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
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}
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/* Return 0 if the address is valid, -errno if not valid */
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static int ls_pcie_addr_valid(struct ls_pcie_rc *pcie_rc, pci_dev_t bdf)
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{
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struct udevice *bus = pcie_rc->bus;
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struct ls_pcie *pcie = pcie_rc->pcie;
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if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
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return -ENODEV;
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if (!pcie_rc->enabled)
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return -ENXIO;
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if (PCI_BUS(bdf) < dev_seq(bus))
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return -EINVAL;
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if ((PCI_BUS(bdf) > dev_seq(bus)) && (!ls_pcie_link_up(pcie)))
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return -EINVAL;
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if (PCI_BUS(bdf) <= (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
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return -EINVAL;
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return 0;
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}
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static int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct ls_pcie_rc *pcie_rc = dev_get_priv(bus);
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struct ls_pcie *pcie = pcie_rc->pcie;
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u32 busdev;
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if (ls_pcie_addr_valid(pcie_rc, bdf))
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return -EINVAL;
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if (PCI_BUS(bdf) == dev_seq(bus)) {
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*paddress = pcie->dbi + offset;
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return 0;
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}
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busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - dev_seq(bus)) |
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PCIE_ATU_DEV(PCI_DEV(bdf)) |
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PCIE_ATU_FUNC(PCI_FUNC(bdf));
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if (PCI_BUS(bdf) == dev_seq(bus) + 1) {
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ls_pcie_cfg0_set_busdev(pcie_rc, busdev);
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*paddress = pcie_rc->cfg0 + offset;
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} else {
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ls_pcie_cfg1_set_busdev(pcie_rc, busdev);
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*paddress = pcie_rc->cfg1 + offset;
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}
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return 0;
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}
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static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
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bdf, offset, valuep, size);
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}
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static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
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bdf, offset, value, size);
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}
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/* Clear multi-function bit */
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static void ls_pcie_clear_multifunction(struct ls_pcie_rc *pcie_rc)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
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}
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/* Fix class value */
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static void ls_pcie_fix_class(struct ls_pcie_rc *pcie_rc)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
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}
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/* Drop MSG TLP except for Vendor MSG */
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static void ls_pcie_drop_msg_tlp(struct ls_pcie_rc *pcie_rc)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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u32 val;
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val = dbi_readl(pcie, PCIE_STRFMR1);
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val &= 0xDFFFFFFF;
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dbi_writel(pcie, val, PCIE_STRFMR1);
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}
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/* Disable all bars in RC mode */
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static void ls_pcie_disable_bars(struct ls_pcie_rc *pcie_rc)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
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dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
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dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
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}
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static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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ls_pcie_setup_atu(pcie_rc);
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ls_pcie_dbi_ro_wr_en(pcie);
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ls_pcie_fix_class(pcie_rc);
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ls_pcie_clear_multifunction(pcie_rc);
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ls_pcie_drop_msg_tlp(pcie_rc);
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ls_pcie_dbi_ro_wr_dis(pcie);
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ls_pcie_disable_bars(pcie_rc);
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}
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static int ls_pcie_probe(struct udevice *dev)
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{
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const struct ls_pcie_drvdata *drvdata = (void *)dev_get_driver_data(dev);
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struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
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const void *fdt = gd->fdt_blob;
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int node = dev_of_offset(dev);
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struct ls_pcie *pcie;
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u16 link_sta;
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uint svr;
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int ret;
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fdt_size_t cfg_size;
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pcie_rc->bus = dev;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie_rc->pcie = pcie;
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/* try resource name of the official binding first */
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"regs", &pcie_rc->dbi_res);
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if (ret)
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"dbi", &pcie_rc->dbi_res);
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if (ret) {
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printf("ls-pcie: resource \"dbi\" not found\n");
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return ret;
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}
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pcie->idx = (pcie_rc->dbi_res.start - PCIE_SYS_BASE_ADDR) /
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PCIE_CCSR_SIZE;
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list_add(&pcie_rc->list, &ls_pcie_list);
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pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
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if (!pcie_rc->enabled) {
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printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
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dev->name);
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return 0;
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}
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pcie->dbi = map_physmem(pcie_rc->dbi_res.start,
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fdt_resource_size(&pcie_rc->dbi_res),
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MAP_NOCACHE);
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pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
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if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
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return 0;
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if (drvdata) {
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pcie->lut = pcie->dbi + drvdata->lut_offset;
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} else {
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"lut", &pcie_rc->lut_res);
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if (!ret)
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pcie->lut = map_physmem(pcie_rc->lut_res.start,
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fdt_resource_size(&pcie_rc->lut_res),
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MAP_NOCACHE);
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}
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if (drvdata) {
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pcie->ctrl = pcie->lut + drvdata->ctrl_offset;
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} else {
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"ctrl", &pcie_rc->ctrl_res);
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if (!ret)
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pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
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fdt_resource_size(&pcie_rc->ctrl_res),
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MAP_NOCACHE);
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if (!pcie->ctrl)
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pcie->ctrl = pcie->lut;
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}
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if (!pcie->ctrl) {
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printf("%s: NOT find CTRL\n", dev->name);
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return -1;
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}
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"config", &pcie_rc->cfg_res);
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if (ret) {
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printf("%s: resource \"config\" not found\n", dev->name);
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return ret;
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}
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cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
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if (cfg_size < SZ_8K) {
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printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
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PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K);
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return 0;
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}
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/*
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* Fix the pcie memory map address and PF control registers address
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* for LS2088A series SoCs
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*/
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svr = get_svr();
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svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A) {
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pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
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pcie->ctrl = pcie->lut + 0x40000;
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}
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pcie_rc->cfg0 = map_physmem(pcie_rc->cfg_res.start,
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fdt_resource_size(&pcie_rc->cfg_res),
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MAP_NOCACHE);
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pcie_rc->cfg1 = pcie_rc->cfg0 +
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fdt_resource_size(&pcie_rc->cfg_res) / 2;
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if (drvdata)
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pcie->big_endian = drvdata->big_endian;
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else
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pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
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debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
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dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
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(unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
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pcie->big_endian);
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printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
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"Root Complex");
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ls_pcie_setup_ctrl(pcie_rc);
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if (!ls_pcie_link_up(pcie)) {
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/* Let the user know there's no PCIe link */
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printf(": no link\n");
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return 0;
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}
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/* Print the negotiated PCIe link width */
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link_sta = readw(pcie->dbi + PCIE_LINK_STA);
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printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
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link_sta & PCIE_LINK_SPEED_MASK);
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return 0;
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}
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static const struct dm_pci_ops ls_pcie_ops = {
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.read_config = ls_pcie_read_config,
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.write_config = ls_pcie_write_config,
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};
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static const struct ls_pcie_drvdata ls1028a_drvdata = {
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.lut_offset = 0x80000,
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.ctrl_offset = 0x40000,
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.big_endian = false,
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};
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static const struct udevice_id ls_pcie_ids[] = {
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{ .compatible = "fsl,ls-pcie" },
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{ .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
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{ }
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};
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U_BOOT_DRIVER(pci_layerscape) = {
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.name = "pci_layerscape",
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.id = UCLASS_PCI,
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.of_match = ls_pcie_ids,
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.ops = &ls_pcie_ops,
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.probe = ls_pcie_probe,
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.priv_auto = sizeof(struct ls_pcie_rc),
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};
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