238 lines
6.3 KiB
C
238 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2018 Xilinx
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*
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* Cadence QSPI controller DMA operations
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*/
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#include <clk.h>
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#include <common.h>
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#include <memalign.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/cache.h>
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#include <cpu_func.h>
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#include <zynqmp_firmware.h>
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#include <asm/arch/hardware.h>
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#include "cadence_qspi.h"
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#include <dt-bindings/power/xlnx-versal-power.h>
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#define CMD_4BYTE_READ 0x13
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#define CMD_4BYTE_FAST_READ 0x0C
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int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op)
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{
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u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
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u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
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n_rx = op->data.nbytes;
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rxbuf = op->data.buf.in;
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rx_rem = n_rx % 4;
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bytes_to_dma = n_rx - rx_rem;
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if (bytes_to_dma) {
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cadence_qspi_apb_enable_linear_mode(false);
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reg = readl(plat->regbase + CQSPI_REG_CONFIG);
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reg |= CQSPI_REG_CONFIG_ENBL_DMA;
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writel(reg, plat->regbase + CQSPI_REG_CONFIG);
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writel(bytes_to_dma, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
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writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE,
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plat->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
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writel(CQSPI_DFLT_DMA_PERIPH_CFG,
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plat->regbase + CQSPI_REG_DMA_PERIPH_CFG);
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writel((unsigned long)rxbuf, plat->regbase +
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CQSPI_DMA_DST_ADDR_REG);
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writel(plat->trigger_address, plat->regbase +
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CQSPI_DMA_SRC_RD_ADDR_REG);
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writel(bytes_to_dma, plat->regbase +
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CQSPI_DMA_DST_SIZE_REG);
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flush_dcache_range((unsigned long)rxbuf,
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(unsigned long)rxbuf + bytes_to_dma);
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writel(CQSPI_DFLT_DST_CTRL_REG_VAL,
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plat->regbase + CQSPI_DMA_DST_CTRL_REG);
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/* Start the indirect read transfer */
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writel(CQSPI_REG_INDIRECTRD_START, plat->regbase +
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CQSPI_REG_INDIRECTRD);
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/* Wait for dma to complete transfer */
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ret = cadence_qspi_apb_wait_for_dma_cmplt(plat);
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if (ret)
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return ret;
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/* Clear indirect completion status */
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writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase +
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CQSPI_REG_INDIRECTRD);
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rxbuf += bytes_to_dma;
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}
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if (rx_rem) {
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reg = readl(plat->regbase + CQSPI_REG_CONFIG);
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reg &= ~CQSPI_REG_CONFIG_ENBL_DMA;
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writel(reg, plat->regbase + CQSPI_REG_CONFIG);
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reg = readl(plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
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reg += bytes_to_dma;
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writel(reg, plat->regbase + CQSPI_REG_CMDADDRESS);
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addr_bytes = readl(plat->regbase + CQSPI_REG_SIZE) &
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CQSPI_REG_SIZE_ADDRESS_MASK;
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opcode = CMD_4BYTE_FAST_READ;
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dummy_cycles = 8;
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writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
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plat->regbase + CQSPI_REG_RD_INSTR);
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reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
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reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
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reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
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CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
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reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
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dummy_cycles = (readl(plat->regbase + CQSPI_REG_RD_INSTR) >>
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CQSPI_REG_RD_INSTR_DUMMY_LSB) &
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CQSPI_REG_RD_INSTR_DUMMY_MASK;
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reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) <<
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CQSPI_REG_CMDCTRL_DUMMY_LSB;
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reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) <<
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CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
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ret = cadence_qspi_apb_exec_flash_cmd(plat->regbase, reg);
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if (ret)
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return ret;
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data = readl(plat->regbase + CQSPI_REG_CMDREADDATALOWER);
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memcpy(rxbuf, &data, rx_rem);
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}
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return 0;
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}
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int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat)
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{
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u32 timeout = CQSPI_DMA_TIMEOUT;
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while (!(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG) &
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CQSPI_DMA_DST_I_STS_DONE) && timeout--)
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udelay(1);
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if (!timeout) {
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printf("DMA timeout\n");
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return -ETIMEDOUT;
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}
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writel(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG),
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plat->regbase + CQSPI_DMA_DST_I_STS_REG);
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return 0;
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}
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#if defined(CONFIG_DM_GPIO)
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int cadence_spi_versal_flash_reset(struct udevice *dev)
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{
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struct gpio_desc gpio;
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u32 reset_gpio;
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int ret;
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/* request gpio and set direction as output set to 1 */
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ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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if (ret) {
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printf("%s: unable to reset ospi flash device", __func__);
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return ret;
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}
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reset_gpio = PMIO_NODE_ID_BASE + gpio.offset;
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/* Request for pin */
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xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL);
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/* Enable hysteresis in cmos receiver */
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xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
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PM_PINCTRL_CONFIG_SCHMITT_CMOS,
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PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL);
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/* Disable Tri-state */
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xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
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PM_PINCTRL_CONFIG_TRI_STATE,
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PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL);
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udelay(1);
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/* Set value 0 to pin */
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dm_gpio_set_value(&gpio, 0);
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udelay(1);
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/* Set value 1 to pin */
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dm_gpio_set_value(&gpio, 1);
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udelay(1);
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return 0;
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}
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#else
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int cadence_spi_versal_flash_reset(struct udevice *dev)
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{
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/* CRP WPROT */
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writel(0, WPROT_CRP);
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/* GPIO Reset */
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writel(0, RST_GPIO);
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/* disable IOU write protection */
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writel(0, WPROT_LPD_MIO);
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/* set direction as output */
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writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)),
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BOOT_MODE_POR_0);
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/* Data output enable */
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writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)),
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BOOT_MODE_POR_1);
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/* IOU SLCR write enable */
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writel(0, WPROT_PMC_MIO);
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/* set MIO as GPIO */
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writel(0x60, MIO_PIN_12);
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/* Set value 1 to pin */
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writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
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udelay(10);
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/* Disable Tri-state */
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writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
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udelay(1);
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/* Set value 0 to pin */
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writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
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udelay(10);
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/* Set value 1 to pin */
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writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
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udelay(10);
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return 0;
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}
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#endif
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void cadence_qspi_apb_enable_linear_mode(bool enable)
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{
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if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) {
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if (enable)
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/* ahb read mode */
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xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
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IOCTL_OSPI_MUX_SELECT,
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PM_OSPI_MUX_SEL_LINEAR, 0, NULL);
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else
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/* DMA mode */
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xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
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IOCTL_OSPI_MUX_SELECT,
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PM_OSPI_MUX_SEL_DMA, 0, NULL);
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} else {
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if (enable)
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writel(readl(VERSAL_AXI_MUX_SEL) |
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VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
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else
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writel(readl(VERSAL_AXI_MUX_SEL) &
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~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
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}
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}
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