162 lines
3.7 KiB
C
162 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Microchip Corporation
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*
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* Author: Clément Léger <clement.leger@bootlin.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#define TCB_CHAN(chan) ((chan) * 0x40)
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#define TCB_CCR(chan) (0x0 + TCB_CHAN(chan))
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#define TCB_CCR_CLKEN (1 << 0)
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#define TCB_CMR(chan) (0x4 + TCB_CHAN(chan))
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#define TCB_CMR_WAVE (1 << 15)
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#define TCB_CMR_TIMER_CLOCK2 1
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#define TCB_CMR_XC1 6
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#define TCB_CMR_ACPA_SET (1 << 16)
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#define TCB_CMR_ACPC_CLEAR (2 << 18)
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#define TCB_CV(chan) (0x10 + TCB_CHAN(chan))
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#define TCB_RA(chan) (0x14 + TCB_CHAN(chan))
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#define TCB_RC(chan) (0x1c + TCB_CHAN(chan))
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#define TCB_IDR(chan) (0x28 + TCB_CHAN(chan))
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#define TCB_BCR 0xc0
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#define TCB_BCR_SYNC (1 << 0)
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#define TCB_BMR 0xc4
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#define TCB_BMR_TC1XC1S_TIOA0 (2 << 2)
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#define TCB_WPMR 0xe4
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#define TCB_WPMR_WAKEY 0x54494d
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#define TCB_CLK_DIVISOR 8
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struct atmel_tcb_plat {
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void __iomem *base;
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};
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static u64 atmel_tcb_get_count(struct udevice *dev)
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{
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struct atmel_tcb_plat *plat = dev_get_plat(dev);
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u64 cv0 = 0;
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u64 cv1 = 0;
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do {
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cv1 = readl(plat->base + TCB_CV(1));
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cv0 = readl(plat->base + TCB_CV(0));
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} while (readl(plat->base + TCB_CV(1)) != cv1);
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cv0 |= cv1 << 32;
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return cv0;
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}
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static void atmel_tcb_configure(void __iomem *base)
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{
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/* Disable write protection */
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writel(TCB_WPMR_WAKEY, base + TCB_WPMR);
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/* Disable all irqs for both channel 0 & 1 */
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writel(0xff, base + TCB_IDR(0));
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writel(0xff, base + TCB_IDR(1));
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/*
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* In order to avoid wrapping, use a 64 bit counter by chaining
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* two channels.
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* Channel 0 is configured to generate a clock on TIOA0 which is cleared
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* when reaching 0x80000000 and set when reaching 0.
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*/
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writel(TCB_CMR_TIMER_CLOCK2 | TCB_CMR_WAVE | TCB_CMR_ACPA_SET
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| TCB_CMR_ACPC_CLEAR, base + TCB_CMR(0));
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writel(0x80000000, base + TCB_RC(0));
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writel(0x1, base + TCB_RA(0));
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writel(TCB_CCR_CLKEN, base + TCB_CCR(0));
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/* Channel 1 is configured to use TIOA0 as input */
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writel(TCB_CMR_XC1 | TCB_CMR_WAVE, base + TCB_CMR(1));
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writel(TCB_CCR_CLKEN, base + TCB_CCR(1));
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/* Set XC1 input to be TIOA0 (ie output of Channel 0) */
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writel(TCB_BMR_TC1XC1S_TIOA0, base + TCB_BMR);
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/* Sync & start all timers */
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writel(TCB_BCR_SYNC, base + TCB_BCR);
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}
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static int atmel_tcb_probe(struct udevice *dev)
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{
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struct atmel_tcb_plat *plat = dev_get_plat(dev);
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct clk clk;
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ulong clk_rate;
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int ret;
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if (!device_is_compatible(dev->parent, "atmel,sama5d2-tcb"))
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return -EINVAL;
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/* Currently, we only support channel 0 and 1 to be chained */
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if (dev_read_addr_index(dev, 0) != 0 &&
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dev_read_addr_index(dev, 1) != 1) {
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printf("Error: only chained timers 0 and 1 are supported\n");
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return -EINVAL;
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}
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ret = clk_get_by_name(dev->parent, "t0_clk", &clk);
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if (ret)
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return -EINVAL;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&clk);
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if (!clk_rate) {
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clk_disable(&clk);
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return -EINVAL;
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}
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uc_priv->clock_rate = clk_rate / TCB_CLK_DIVISOR;
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atmel_tcb_configure(plat->base);
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return 0;
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}
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static int atmel_tcb_of_to_plat(struct udevice *dev)
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{
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struct atmel_tcb_plat *plat = dev_get_plat(dev);
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plat->base = dev_read_addr_ptr(dev->parent);
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return 0;
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}
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static const struct timer_ops atmel_tcb_ops = {
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.get_count = atmel_tcb_get_count,
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};
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static const struct udevice_id atmel_tcb_ids[] = {
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{ .compatible = "atmel,tcb-timer" },
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{ }
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};
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U_BOOT_DRIVER(atmel_tcb) = {
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.name = "atmel_tcb",
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.id = UCLASS_TIMER,
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.of_match = atmel_tcb_ids,
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.of_to_plat = atmel_tcb_of_to_plat,
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.plat_auto = sizeof(struct atmel_tcb_plat),
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.probe = atmel_tcb_probe,
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.ops = &atmel_tcb_ops,
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};
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