390 lines
8.9 KiB
C
390 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
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* Author: Elaine <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_NPLL 4
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#define APLL_BOOST_H 5
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#define APLL_BOOST_L 6
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#define ARMCLK 7
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/* sclk gates (special clocks) */
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#define USB480M 14
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#define SCLK_PDM 15
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#define SCLK_I2S0_TX 16
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#define SCLK_I2S0_TX_OUT 17
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#define SCLK_I2S0_RX 18
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#define SCLK_I2S0_RX_OUT 19
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#define SCLK_I2S1 20
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#define SCLK_I2S1_OUT 21
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#define SCLK_I2S2 22
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#define SCLK_I2S2_OUT 23
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#define SCLK_UART1 24
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#define SCLK_UART2 25
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#define SCLK_UART3 26
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#define SCLK_UART4 27
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#define SCLK_UART5 28
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#define SCLK_I2C0 29
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#define SCLK_I2C1 30
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#define SCLK_I2C2 31
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#define SCLK_I2C3 32
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#define SCLK_I2C4 33
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#define SCLK_PWM0 34
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#define SCLK_PWM1 35
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#define SCLK_SPI0 36
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#define SCLK_SPI1 37
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#define SCLK_TIMER0 38
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#define SCLK_TIMER1 39
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#define SCLK_TIMER2 40
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#define SCLK_TIMER3 41
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#define SCLK_TIMER4 42
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#define SCLK_TIMER5 43
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#define SCLK_TSADC 44
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#define SCLK_SARADC 45
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#define SCLK_OTP 46
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#define SCLK_OTP_USR 47
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#define SCLK_CRYPTO 48
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#define SCLK_CRYPTO_APK 49
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#define SCLK_DDRC 50
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#define SCLK_ISP 51
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#define SCLK_CIF_OUT 52
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#define SCLK_RGA_CORE 53
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#define SCLK_VOPB_PWM 54
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#define SCLK_NANDC 55
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#define SCLK_SDIO 56
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#define SCLK_EMMC 57
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#define SCLK_SFC 58
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#define SCLK_SDMMC 59
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#define SCLK_OTG_ADP 60
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#define SCLK_GMAC_SRC 61
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#define SCLK_GMAC 62
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#define SCLK_GMAC_RX_TX 63
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#define SCLK_MAC_REF 64
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#define SCLK_MAC_REFOUT 65
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#define SCLK_MAC_OUT 66
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#define SCLK_SDMMC_DRV 67
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#define SCLK_SDMMC_SAMPLE 68
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#define SCLK_SDIO_DRV 69
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#define SCLK_SDIO_SAMPLE 70
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#define SCLK_EMMC_DRV 71
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#define SCLK_EMMC_SAMPLE 72
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#define SCLK_GPU 73
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#define SCLK_PVTM 74
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#define SCLK_CORE_VPU 75
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#define SCLK_GMAC_RMII 76
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#define SCLK_UART2_SRC 77
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#define SCLK_NANDC_DIV 78
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#define SCLK_NANDC_DIV50 79
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#define SCLK_SDIO_DIV 80
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#define SCLK_SDIO_DIV50 81
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#define SCLK_EMMC_DIV 82
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#define SCLK_EMMC_DIV50 83
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/* dclk gates */
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#define DCLK_VOPB 150
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#define DCLK_VOPL 151
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/* aclk gates */
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#define ACLK_GPU 170
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#define ACLK_BUS_PRE 171
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#define ACLK_CRYPTO 172
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#define ACLK_VI_PRE 173
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#define ACLK_VO_PRE 174
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#define ACLK_VPU 175
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#define ACLK_PERI_PRE 176
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#define ACLK_GMAC 178
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#define ACLK_CIF 179
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#define ACLK_ISP 180
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#define ACLK_VOPB 181
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#define ACLK_VOPL 182
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#define ACLK_RGA 183
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#define ACLK_GIC 184
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#define ACLK_DCF 186
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#define ACLK_DMAC 187
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/* hclk gates */
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#define HCLK_BUS_PRE 240
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#define HCLK_CRYPTO 241
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#define HCLK_VI_PRE 242
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#define HCLK_VO_PRE 243
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#define HCLK_VPU 244
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#define HCLK_PERI_PRE 245
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#define HCLK_MMC_NAND 246
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#define HCLK_SDMMC 247
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#define HCLK_USB 248
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#define HCLK_CIF 249
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#define HCLK_ISP 250
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#define HCLK_VOPB 251
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#define HCLK_VOPL 252
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#define HCLK_RGA 253
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#define HCLK_NANDC 254
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#define HCLK_SDIO 255
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#define HCLK_EMMC 256
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#define HCLK_SFC 257
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#define HCLK_OTG 258
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#define HCLK_HOST 259
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#define HCLK_HOST_ARB 260
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#define HCLK_PDM 261
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#define HCLK_I2S0 262
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#define HCLK_I2S1 263
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#define HCLK_I2S2 264
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/* pclk gates */
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#define PCLK_BUS_PRE 320
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#define PCLK_DDR 321
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#define PCLK_VO_PRE 322
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#define PCLK_GMAC 323
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#define PCLK_MIPI_DSI 324
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#define PCLK_MIPIDSIPHY 325
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#define PCLK_MIPICSIPHY 326
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#define PCLK_USB_GRF 327
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#define PCLK_DCF 328
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#define PCLK_UART1 329
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#define PCLK_UART2 330
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#define PCLK_UART3 331
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#define PCLK_UART4 332
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#define PCLK_UART5 333
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#define PCLK_I2C0 334
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#define PCLK_I2C1 335
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#define PCLK_I2C2 336
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#define PCLK_I2C3 337
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#define PCLK_I2C4 338
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#define PCLK_PWM0 339
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#define PCLK_PWM1 340
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#define PCLK_SPI0 341
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#define PCLK_SPI1 342
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#define PCLK_SARADC 343
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#define PCLK_TSADC 344
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#define PCLK_TIMER 345
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#define PCLK_OTP_NS 346
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#define PCLK_WDT_NS 347
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#define PCLK_GPIO1 348
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#define PCLK_GPIO2 349
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#define PCLK_GPIO3 350
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#define PCLK_ISP 351
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#define PCLK_CIF 352
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#define PCLK_OTP_PHY 353
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#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
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/* pmu-clocks indices */
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#define PLL_GPLL 1
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#define SCLK_RTC32K_PMU 4
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#define SCLK_WIFI_PMU 5
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#define SCLK_UART0_PMU 6
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#define SCLK_PVTM_PMU 7
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#define PCLK_PMU_PRE 8
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#define SCLK_REF24M_PMU 9
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#define SCLK_USBPHY_REF 10
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#define SCLK_MIPIDSIPHY_REF 11
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#define XIN24M_DIV 12
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#define PCLK_GPIO0_PMU 20
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#define PCLK_UART0_PMU 21
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#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
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/* soft-reset indices */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE2_DBG 10
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#define SRST_CORE3_DBG 11
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#define SRST_TOPDBG 12
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#define SRST_CORE_NOC 13
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#define SRST_STRC_A 14
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#define SRST_L2C 15
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#define SRST_DAP 16
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#define SRST_CORE_PVTM 17
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#define SRST_GPU 18
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#define SRST_GPU_NIU 19
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#define SRST_UPCTL2 20
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#define SRST_UPCTL2_A 21
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#define SRST_UPCTL2_P 22
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#define SRST_MSCH 23
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#define SRST_MSCH_P 24
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#define SRST_DDRMON_P 25
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#define SRST_DDRSTDBY_P 26
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#define SRST_DDRSTDBY 27
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#define SRST_DDRGRF_p 28
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#define SRST_AXI_SPLIT_A 29
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#define SRST_AXI_CMD_A 30
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#define SRST_AXI_CMD_P 31
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#define SRST_DDRPHY 32
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#define SRST_DDRPHYDIV 33
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#define SRST_DDRPHY_P 34
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#define SRST_VPU_A 36
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#define SRST_VPU_NIU_A 37
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#define SRST_VPU_H 38
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#define SRST_VPU_NIU_H 39
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#define SRST_VI_NIU_A 40
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#define SRST_VI_NIU_H 41
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#define SRST_ISP_H 42
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#define SRST_ISP 43
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#define SRST_CIF_A 44
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#define SRST_CIF_H 45
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#define SRST_CIF_PCLKIN 46
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#define SRST_MIPICSIPHY_P 47
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#define SRST_VO_NIU_A 48
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#define SRST_VO_NIU_H 49
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#define SRST_VO_NIU_P 50
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#define SRST_VOPB_A 51
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#define SRST_VOPB_H 52
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#define SRST_VOPB 53
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#define SRST_PWM_VOPB 54
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#define SRST_VOPL_A 55
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#define SRST_VOPL_H 56
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#define SRST_VOPL 57
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#define SRST_RGA_A 58
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#define SRST_RGA_H 59
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#define SRST_RGA 60
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#define SRST_MIPIDSI_HOST_P 61
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#define SRST_MIPIDSIPHY_P 62
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#define SRST_VPU_CORE 63
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#define SRST_PERI_NIU_A 64
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#define SRST_USB_NIU_H 65
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#define SRST_USB2OTG_H 66
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#define SRST_USB2OTG 67
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#define SRST_USB2OTG_ADP 68
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#define SRST_USB2HOST_H 69
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#define SRST_USB2HOST_ARB_H 70
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#define SRST_USB2HOST_AUX_H 71
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#define SRST_USB2HOST_EHCI 72
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#define SRST_USB2HOST 73
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#define SRST_USBPHYPOR 74
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#define SRST_USBPHY_OTG_PORT 75
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#define SRST_USBPHY_HOST_PORT 76
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#define SRST_USBPHY_GRF 77
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#define SRST_CPU_BOOST_P 78
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#define SRST_CPU_BOOST 79
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#define SRST_MMC_NAND_NIU_H 80
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#define SRST_SDIO_H 81
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#define SRST_EMMC_H 82
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#define SRST_SFC_H 83
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#define SRST_SFC 84
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#define SRST_SDCARD_NIU_H 85
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#define SRST_SDMMC_H 86
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#define SRST_NANDC_H 89
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#define SRST_NANDC 90
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#define SRST_GMAC_NIU_A 92
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#define SRST_GMAC_NIU_P 93
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#define SRST_GMAC_A 94
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#define SRST_PMU_NIU_P 96
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#define SRST_PMU_SGRF_P 97
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#define SRST_PMU_GRF_P 98
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#define SRST_PMU 99
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#define SRST_PMU_MEM_P 100
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#define SRST_PMU_GPIO0_P 101
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#define SRST_PMU_UART0_P 102
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#define SRST_PMU_CRU_P 103
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#define SRST_PMU_PVTM 104
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#define SRST_PMU_UART 105
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#define SRST_PMU_NIU_H 106
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#define SRST_PMU_DDR_FAIL_SAVE 107
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#define SRST_PMU_CORE_PERF_A 108
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#define SRST_PMU_CORE_GRF_P 109
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#define SRST_PMU_GPU_PERF_A 110
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#define SRST_PMU_GPU_GRF_P 111
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#define SRST_CRYPTO_NIU_A 112
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#define SRST_CRYPTO_NIU_H 113
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#define SRST_CRYPTO_A 114
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#define SRST_CRYPTO_H 115
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#define SRST_CRYPTO 116
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#define SRST_CRYPTO_APK 117
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#define SRST_BUS_NIU_H 120
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#define SRST_USB_NIU_P 121
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#define SRST_BUS_TOP_NIU_P 122
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#define SRST_INTMEM_A 123
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#define SRST_GIC_A 124
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#define SRST_ROM_H 126
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#define SRST_DCF_A 127
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#define SRST_DCF_P 128
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#define SRST_PDM_H 129
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#define SRST_PDM 130
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#define SRST_I2S0_H 131
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#define SRST_I2S0_TX 132
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#define SRST_I2S1_H 133
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#define SRST_I2S1 134
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#define SRST_I2S2_H 135
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#define SRST_I2S2 136
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#define SRST_UART1_P 137
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#define SRST_UART1 138
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#define SRST_UART2_P 139
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#define SRST_UART2 140
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#define SRST_UART3_P 141
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#define SRST_UART3 142
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#define SRST_UART4_P 143
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#define SRST_UART4 144
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#define SRST_UART5_P 145
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#define SRST_UART5 146
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#define SRST_I2C0_P 147
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#define SRST_I2C0 148
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#define SRST_I2C1_P 149
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#define SRST_I2C1 150
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#define SRST_I2C2_P 151
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#define SRST_I2C2 152
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#define SRST_I2C3_P 153
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#define SRST_I2C3 154
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#define SRST_PWM0_P 157
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#define SRST_PWM0 158
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#define SRST_PWM1_P 159
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#define SRST_PWM1 160
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#define SRST_SPI0_P 161
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#define SRST_SPI0 162
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#define SRST_SPI1_P 163
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#define SRST_SPI1 164
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#define SRST_SARADC_P 165
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#define SRST_SARADC 166
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#define SRST_TSADC_P 167
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#define SRST_TSADC 168
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#define SRST_TIMER_P 169
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#define SRST_TIMER0 170
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#define SRST_TIMER1 171
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#define SRST_TIMER2 172
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#define SRST_TIMER3 173
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#define SRST_TIMER4 174
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#define SRST_TIMER5 175
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#define SRST_OTP_NS_P 176
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#define SRST_OTP_NS_SBPI 177
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#define SRST_OTP_NS_USR 178
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#define SRST_OTP_PHY_P 179
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#define SRST_OTP_PHY 180
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#define SRST_WDT_NS_P 181
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#define SRST_GPIO1_P 182
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#define SRST_GPIO2_P 183
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#define SRST_GPIO3_P 184
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#define SRST_SGRF_P 185
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#define SRST_GRF_P 186
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#define SRST_I2S0_RX 191
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#endif
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