161 lines
3.4 KiB
C
161 lines
3.4 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef FSL_MMDC_H
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#define FSL_MMDC_H
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#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
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#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
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#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
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#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
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#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680
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#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
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#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
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#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
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#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
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#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
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#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
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#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
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/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
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#define WR_LVL_HW_EN 0x00000001
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/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
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#define MPR_COMPARE_EN 0x00000001
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#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
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/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
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#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
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/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
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#define AUTO_RD_CALIBRATION_EN 0x00000010
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#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
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#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
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#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000
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#define START_REFRESH 0x00000001
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/* MMDC Core Special Command Register (MDSCR) */
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#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
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#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
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#define DISABLE_CFG_REQ 0x0
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#define CONFIGURATION_REQ (0x1 << 15)
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#define WL_EN (0x1 << 9)
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#define CMD_NORMAL (0x0 << 4)
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#define CMD_PRECHARGE (0x1 << 4)
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#define CMD_AUTO_REFRESH (0x2 << 4)
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#define CMD_LOAD_MODE_REG (0x3 << 4)
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#define CMD_ZQ_CALIBRATION (0x4 << 4)
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#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
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#define CMD_MRR (0x6 << 4)
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#define CMD_BANK_ADDR_0 0x0
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#define CMD_BANK_ADDR_1 0x1
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#define CMD_BANK_ADDR_2 0x2
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#define CMD_BANK_ADDR_3 0x3
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#define CMD_BANK_ADDR_4 0x4
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#define CMD_BANK_ADDR_5 0x5
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#define CMD_BANK_ADDR_6 0x6
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#define CMD_BANK_ADDR_7 0x7
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/* MMDC Registers */
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struct mmdc_p_regs {
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u32 mdctl;
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u32 mdpdc;
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u32 mdotc;
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u32 mdcfg0;
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u32 mdcfg1;
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u32 mdcfg2;
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u32 mdmisc;
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u32 mdscr;
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u32 mdref;
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u32 res1[2];
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u32 mdrwd;
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u32 mdor;
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u32 mdmrr;
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u32 mdcfg3lp;
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u32 mdmr4;
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u32 mdasp;
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u32 res2[239];
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u32 maarcr;
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u32 mapsr;
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u32 maexidr0;
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u32 maexidr1;
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u32 madpcr0;
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u32 madpcr1;
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u32 madpsr0;
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u32 madpsr1;
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u32 madpsr2;
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u32 madpsr3;
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u32 madpsr4;
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u32 madpsr5;
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u32 masbs0;
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u32 masbs1;
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u32 res3[2];
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u32 magenp;
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u32 res4[239];
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u32 mpzqhwctrl;
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u32 mpzqswctrl;
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u32 mpwlgcr;
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u32 mpwldectrl0;
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u32 mpwldectrl1;
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u32 mpwldlst;
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u32 mpodtctrl;
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u32 mprddqby0dl;
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u32 mprddqby1dl;
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u32 mprddqby2dl;
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u32 mprddqby3dl;
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u32 res5[4];
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u32 mpdgctrl0;
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u32 mpdgctrl1;
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u32 mpdgdlst0;
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u32 mprddlctl;
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u32 mprddlst;
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u32 mpwrdlctl;
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u32 mpwrdlst;
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u32 mpsdctrl;
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u32 mpzqlp2ctl;
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u32 mprddlhwctl;
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u32 mpwrdlhwctl;
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u32 mprddlhwst0;
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u32 mprddlhwst1;
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u32 mpwrdlhwst0;
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u32 mpwrdlhwst1;
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u32 mpwlhwerr;
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u32 mpdghwst0;
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u32 mpdghwst1;
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u32 mpdghwst2;
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u32 mpdghwst3;
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u32 mppdcmpr1;
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u32 mppdcmpr2;
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u32 mpswdar0;
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u32 mpswdrdr0;
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u32 mpswdrdr1;
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u32 mpswdrdr2;
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u32 mpswdrdr3;
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u32 mpswdrdr4;
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u32 mpswdrdr5;
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u32 mpswdrdr6;
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u32 mpswdrdr7;
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u32 mpmur0;
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u32 mpwrcadl;
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u32 mpdccr;
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};
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#endif /* FSL_MMDC_H */
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