75 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			75 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * Copyright 2017 NXP
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|  */
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| 
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| #ifndef __FSL_QBMAN_H__
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| #define __FSL_QBMAN_H__
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| void fdt_fixup_qportals(void *blob);
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| void fdt_fixup_bportals(void *blob);
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| void inhibit_portals(void __iomem *addr, int max_portals,
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| 		     int arch_max_portals, int portal_cinh_size);
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| void setup_qbman_portals(void);
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| 
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| struct ccsr_qman {
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| #ifdef CONFIG_SYS_FSL_QMAN_V3
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| 	u8	res0[0x200];
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| #else
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| 	struct {
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| 		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
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| 		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
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| 		u32	res;
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| 		u32	qcsp_dd_cfg;	/* 0xc - SW Portal Dynamic Debug cfg */
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| 	} qcsp[32];
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| #endif
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| 	/* Not actually reserved, but irrelevant to u-boot */
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| 	u8	res[0xbf8 - 0x200];
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| 	u32	ip_rev_1;
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| 	u32	ip_rev_2;
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| 	u32	fqd_bare;	/* FQD Extended Base Addr Register */
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| 	u32	fqd_bar;	/* FQD Base Addr Register */
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| 	u8	res1[0x8];
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| 	u32	fqd_ar;		/* FQD Attributes Register */
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| 	u8	res2[0xc];
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| 	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
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| 	u32	pfdr_bar;	/* PFDR Base Addr Register */
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| 	u8	res3[0x8];
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| 	u32	pfdr_ar;	/* PFDR Attributes Register */
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| 	u8	res4[0x4c];
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| 	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
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| 	u32	qcsp_bar;	/* QCSP Base Addr Register */
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| 	u8	res5[0x78];
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| 	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
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| 	u32	srcidr;		/* Source ID Register */
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| 	u32	liodnr;		/* LIODN Register */
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| 	u8	res6[4];
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| 	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
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| 	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
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| 	u8	res7[0x2e8];
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| #ifdef CONFIG_SYS_FSL_QMAN_V3
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| 	struct {
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| 		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
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| 		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
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| 		u32	res;
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| 		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
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| 	} qcsp[50];
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| #endif
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| };
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| 
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| struct ccsr_bman {
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| 	/* Not actually reserved, but irrelevant to u-boot */
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| 	u8	res[0xbf8];
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| 	u32	ip_rev_1;
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| 	u32	ip_rev_2;
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| 	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
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| 	u32	fbpr_bar;	/* FBPR Base Addr Register */
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| 	u8	res1[0x8];
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| 	u32	fbpr_ar;	/* FBPR Attributes Register */
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| 	u8	res2[0xf0];
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| 	u32	srcidr;		/* Source ID Register */
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| 	u32	liodnr;		/* LIODN Register */
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| 	u8	res7[0x2f4];
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| };
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| 
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| #endif /* __FSL_QBMAN_H__ */
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