Sean Anderson 404339759e riscv: Remove unnecessary instruction ... The add instruction on risc-v can have any three sources and targets, so there is no need for an intermediate mov. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2020-02-10 14:51:52 +08:00
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ax25	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	2019-12-10 08:23:10 +08:00
generic	common: Move board_get_usable_ram_top() out of common.h	2019-12-02 18:25:04 -05:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
cpu.c	riscv: add run mode configuration for SPL	2019-08-26 16:07:42 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: Remove unnecessary instruction	2020-02-10 14:51:52 +08:00
u-boot-spl.lds	riscv: Fix clear bss loop in the start-up code	2019-12-10 08:23:10 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00