439 lines
10 KiB
C
439 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/ccm_regs.h>
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#include <asm/global_data.h>
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#include <linux/iopoll.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
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static enum ccm_clk_src clk_root_mux[][4] = {
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{ OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, SYS_PLL_PFD2 }, /* bus */
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{ OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, SYS_PLL_PFD2_DIV2 }, /* non-IO */
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{ OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, VIDEO_PLL_CLK }, /* IO*/
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{ OSC_24M_CLK, SYS_PLL_PFD0, AUDIO_PLL_CLK, EXT_CLK }, /* TPM */
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{ OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, EXT_CLK }, /* Audio */
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{ OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD0 }, /* Video */
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{ OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, AUDIO_PLL_CLK }, /* CKO1 */
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{ OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, VIDEO_PLL_CLK }, /* CKO2 */
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{ OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD2 }, /* CAMSCAN */
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};
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static struct clk_root_map clk_root_array[] = {
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{ ARM_A55_PERIPH_CLK_ROOT, 0 },
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{ ARM_A55_MTR_BUS_CLK_ROOT, 2 },
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{ ARM_A55_CLK_ROOT, 0 },
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{ M33_CLK_ROOT, 2 },
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{ SENTINEL_CLK_ROOT, 2 },
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{ BUS_WAKEUP_CLK_ROOT, 2 },
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{ BUS_AON_CLK_ROOT, 2 },
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{ WAKEUP_AXI_CLK_ROOT, 0 },
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{ SWO_TRACE_CLK_ROOT, 2 },
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{ M33_SYSTICK_CLK_ROOT, 2 },
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{ FLEXIO1_CLK_ROOT, 2 },
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{ FLEXIO2_CLK_ROOT, 2 },
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{ LPIT1_CLK_ROOT, 2 },
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{ LPIT2_CLK_ROOT, 2 },
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{ LPTMR1_CLK_ROOT, 2 },
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{ LPTMR2_CLK_ROOT, 2 },
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{ TPM1_CLK_ROOT, 3 },
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{ TPM2_CLK_ROOT, 3 },
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{ TPM3_CLK_ROOT, 3 },
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{ TPM4_CLK_ROOT, 3 },
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{ TPM5_CLK_ROOT, 3 },
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{ TPM6_CLK_ROOT, 3 },
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{ FLEXSPI1_CLK_ROOT, 0 },
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{ CAN1_CLK_ROOT, 2 },
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{ CAN2_CLK_ROOT, 2 },
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{ LPUART1_CLK_ROOT, 2 },
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{ LPUART2_CLK_ROOT, 2 },
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{ LPUART3_CLK_ROOT, 2 },
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{ LPUART4_CLK_ROOT, 2 },
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{ LPUART5_CLK_ROOT, 2 },
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{ LPUART6_CLK_ROOT, 2 },
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{ LPUART7_CLK_ROOT, 2 },
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{ LPUART8_CLK_ROOT, 2 },
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{ LPI2C1_CLK_ROOT, 2 },
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{ LPI2C2_CLK_ROOT, 2 },
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{ LPI2C3_CLK_ROOT, 2 },
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{ LPI2C4_CLK_ROOT, 2 },
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{ LPI2C5_CLK_ROOT, 2 },
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{ LPI2C6_CLK_ROOT, 2 },
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{ LPI2C7_CLK_ROOT, 2 },
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{ LPI2C8_CLK_ROOT, 2 },
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{ LPSPI1_CLK_ROOT, 2 },
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{ LPSPI2_CLK_ROOT, 2 },
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{ LPSPI3_CLK_ROOT, 2 },
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{ LPSPI4_CLK_ROOT, 2 },
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{ LPSPI5_CLK_ROOT, 2 },
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{ LPSPI6_CLK_ROOT, 2 },
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{ LPSPI7_CLK_ROOT, 2 },
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{ LPSPI8_CLK_ROOT, 2 },
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{ I3C1_CLK_ROOT, 2 },
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{ I3C2_CLK_ROOT, 2 },
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{ USDHC1_CLK_ROOT, 0 },
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{ USDHC2_CLK_ROOT, 0 },
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{ USDHC3_CLK_ROOT, 0 },
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{ SAI1_CLK_ROOT, 4 },
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{ SAI2_CLK_ROOT, 4 },
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{ SAI3_CLK_ROOT, 4 },
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{ CCM_CKO1_CLK_ROOT, 6 },
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{ CCM_CKO2_CLK_ROOT, 7 },
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{ CCM_CKO3_CLK_ROOT, 6 },
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{ CCM_CKO4_CLK_ROOT, 7 },
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{ HSIO_CLK_ROOT, 2 },
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{ HSIO_USB_TEST_60M_CLK_ROOT, 2 },
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{ HSIO_ACSCAN_80M_CLK_ROOT, 2 },
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{ HSIO_ACSCAN_480M_CLK_ROOT, 0 },
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{ NIC_CLK_ROOT, 0 },
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{ NIC_APB_CLK_ROOT, 2 },
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{ ML_APB_CLK_ROOT, 2 },
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{ ML_CLK_ROOT, 0 },
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{ MEDIA_AXI_CLK_ROOT, 0 },
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{ MEDIA_APB_CLK_ROOT, 2 },
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{ MEDIA_LDB_CLK_ROOT, 5 },
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{ MEDIA_DISP_PIX_CLK_ROOT, 5 },
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{ CAM_PIX_CLK_ROOT, 5 },
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{ MIPI_TEST_BYTE_CLK_ROOT, 5 },
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{ MIPI_PHY_CFG_CLK_ROOT, 5 },
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{ DRAM_ALT_CLK_ROOT, 0 },
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{ DRAM_APB_CLK_ROOT, 1 },
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{ ADC_CLK_ROOT, 2 },
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{ PDM_CLK_ROOT, 4 },
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{ TSTMR1_CLK_ROOT, 2 },
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{ TSTMR2_CLK_ROOT, 2 },
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{ MQS1_CLK_ROOT, 4 },
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{ MQS2_CLK_ROOT, 4 },
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{ AUDIO_XCVR_CLK_ROOT, 1 },
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{ SPDIF_CLK_ROOT, 4 },
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{ ENET_CLK_ROOT, 1 },
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{ ENET_TIMER1_CLK_ROOT, 2 },
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{ ENET_TIMER2_CLK_ROOT, 2 },
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{ ENET_REF_CLK_ROOT, 1 },
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{ ENET_REF_PHY_CLK_ROOT, 2 },
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{ I3C1_SLOW_CLK_ROOT, 2 },
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{ I3C2_SLOW_CLK_ROOT, 2 },
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{ USB_PHY_BURUNIN_CLK_ROOT, 2 },
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{ PAL_CAME_SCAN_CLK_ROOT, 8 },
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};
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int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable)
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{
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u32 authen;
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if (oscpll >= OSCPLL_END)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
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/* If using cpulpm, need disable it first */
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if (authen & CCM_AUTHEN_CPULPM_MODE)
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return -EPERM;
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if (enable)
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writel(1, &ccm_reg->clk_oscplls[oscpll].direct);
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else
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writel(0, &ccm_reg->clk_oscplls[oscpll].direct);
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return 0;
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}
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/* auto mode, enable = DIRECT[ON] | STATUS0[IN_USE] */
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int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable)
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{
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u32 authen;
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if (oscpll >= OSCPLL_END)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
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/* AUTO CTRL and CPULPM are mutual exclusion, need disable CPULPM first */
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if (authen & CCM_AUTHEN_CPULPM_MODE)
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return -EPERM;
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if (enable)
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writel(authen | CCM_AUTHEN_AUTO_CTRL, &ccm_reg->clk_oscplls[oscpll].authen);
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else
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writel((authen & ~CCM_AUTHEN_AUTO_CTRL), &ccm_reg->clk_oscplls[oscpll].authen);
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return 0;
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}
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int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable)
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{
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u32 authen;
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if (oscpll >= OSCPLL_END)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
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/* AUTO CTRL and CPULPM are mutual exclusion, need disable AUTO CTRL first */
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if (authen & CCM_AUTHEN_AUTO_CTRL)
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return -EPERM;
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if (enable)
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writel(authen | CCM_AUTHEN_CPULPM_MODE, &ccm_reg->clk_oscplls[oscpll].authen);
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else
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writel((authen & ~CCM_AUTHEN_CPULPM_MODE), &ccm_reg->clk_oscplls[oscpll].authen);
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return 0;
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}
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int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val)
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{
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u32 lpm, authen;
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if (oscpll >= OSCPLL_END || domain >= 16)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
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if (!(authen & CCM_AUTHEN_CPULPM_MODE))
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return -EPERM;
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if (domain > 7) {
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lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm1);
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lpm &= ~(0x3 << ((domain - 8) * 4));
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lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
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writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm1);
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} else {
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lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm0);
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lpm &= ~(0x3 << (domain * 4));
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lpm |= (lpm_val & 0x3) << (domain * 4);
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writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm0);
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}
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return 0;
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}
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bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll)
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{
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return !!(readl(&ccm_reg->clk_oscplls[oscpll].status0) & 0x1);
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}
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int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, bool non_secure, bool user_mode, bool lock_tz)
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{
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u32 authen;
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if (oscpll >= OSCPLL_END)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
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authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
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authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
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authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
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writel(authen, &ccm_reg->clk_oscplls[oscpll].authen);
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return 0;
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}
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int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div)
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{
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int i;
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int ret;
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u32 mux, status;
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if (clk_root_id >= CLK_ROOT_NUM || div > 256 || div == 0)
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return -EINVAL;
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mux = clk_root_array[clk_root_id].mux_type;
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for (i = 0; i < 4; i++) {
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if (src == clk_root_mux[mux][i])
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break;
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}
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if (i == 4) {
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printf("Invalid source [%u] for this clk root\n", src);
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return -EINVAL;
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}
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writel((i << 8) | (div - 1), &ccm_reg->clk_roots[clk_root_id].control);
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ret = readl_poll_timeout(&ccm_reg->clk_roots[clk_root_id].status0, status,
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!(status & CLK_ROOT_STATUS_CHANGING), 200000);
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if (ret)
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printf("%s: failed, status: 0x%x\n", __func__,
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readl(&ccm_reg->clk_roots[clk_root_id].status0));
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return ret;
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};
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u32 ccm_clk_root_get_rate(u32 clk_root_id)
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{
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u32 mux, status, div, rate;
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enum ccm_clk_src src;
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if (clk_root_id >= CLK_ROOT_NUM)
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return 0;
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status = readl(&ccm_reg->clk_roots[clk_root_id].control);
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if (status & CLK_ROOT_STATUS_OFF)
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return 0; /* clock is off */
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mux = (status & CLK_ROOT_MUX_MASK) >> CLK_ROOT_MUX_SHIFT;
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div = status & CLK_ROOT_DIV_MASK;
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src = clk_root_mux[clk_root_array[clk_root_id].mux_type][mux];
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rate = get_clk_src_rate(src) * 1000;
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return rate / (div + 1); /* return in hz */
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}
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int ccm_clk_root_tz_access(u32 clk_root_id, bool non_secure, bool user_mode, bool lock_tz)
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{
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u32 authen;
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if (clk_root_id >= CLK_ROOT_NUM)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_roots[clk_root_id].authen);
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authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
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authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
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authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
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writel(authen, &ccm_reg->clk_roots[clk_root_id].authen);
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return 0;
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}
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int ccm_lpcg_on(u32 lpcg, bool enable)
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{
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u32 authen;
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if (lpcg >= CCGR_NUM)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
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/* If using cpulpm, need disable it first */
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if (authen & CCM_AUTHEN_CPULPM_MODE)
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return -EPERM;
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if (enable)
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writel(1, &ccm_reg->clk_lpcgs[lpcg].direct);
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else
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writel(0, &ccm_reg->clk_lpcgs[lpcg].direct);
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return 0;
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}
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int ccm_lpcg_lpm(u32 lpcg, bool enable)
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{
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u32 authen;
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if (lpcg >= CCGR_NUM)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
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if (enable)
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writel(authen | CCM_AUTHEN_CPULPM_MODE, &ccm_reg->clk_lpcgs[lpcg].authen);
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else
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writel((authen & ~CCM_AUTHEN_CPULPM_MODE), &ccm_reg->clk_lpcgs[lpcg].authen);
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return 0;
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}
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int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val)
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{
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u32 lpm, authen;
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if (lpcg >= CCGR_NUM || domain >= 16)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
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if (!(authen & CCM_AUTHEN_CPULPM_MODE))
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return -EPERM;
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if (domain > 7) {
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lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm1);
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lpm &= ~(0x3 << ((domain - 8) * 4));
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lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
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writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm1);
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} else {
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lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm0);
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lpm &= ~(0x3 << (domain * 4));
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lpm |= (lpm_val & 0x3) << (domain * 4);
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writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm0);
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}
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return 0;
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}
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bool ccm_lpcg_is_clk_on(u32 lpcg)
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{
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return !!(readl(&ccm_reg->clk_lpcgs[lpcg].status0) & 0x1);
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}
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int ccm_lpcg_tz_access(u32 lpcg, bool non_secure, bool user_mode, bool lock_tz)
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{
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u32 authen;
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if (lpcg >= CCGR_NUM)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
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authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
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authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
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authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
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writel(authen, &ccm_reg->clk_lpcgs[lpcg].authen);
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return 0;
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}
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int ccm_shared_gpr_set(u32 gpr, u32 val)
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{
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if (gpr >= SHARED_GPR_NUM)
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return -EINVAL;
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writel(val, &ccm_reg->clk_shared_gpr[gpr].gpr);
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return 0;
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}
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int ccm_shared_gpr_get(u32 gpr, u32 *val)
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{
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if (gpr >= SHARED_GPR_NUM || !val)
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return -EINVAL;
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*val = readl(&ccm_reg->clk_shared_gpr[gpr].gpr);
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return 0;
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}
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int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock_tz)
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{
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u32 authen;
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if (gpr >= SHARED_GPR_NUM)
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return -EINVAL;
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authen = readl(&ccm_reg->clk_shared_gpr[gpr].authen);
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authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
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authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
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authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
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writel(authen, &ccm_reg->clk_shared_gpr[gpr].authen);
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return 0;
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}
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