354 lines
9.4 KiB
C
354 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef NICVF_QUEUES_H
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#define NICVF_QUEUES_H
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#include "q_struct.h"
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#define MAX_QUEUE_SET 128
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#define MAX_RCV_QUEUES_PER_QS 8
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#define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
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#define MAX_SND_QUEUES_PER_QS 8
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#define MAX_CMP_QUEUES_PER_QS 8
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/* VF's queue interrupt ranges */
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#define NICVF_INTR_ID_CQ 0
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#define NICVF_INTR_ID_SQ 8
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#define NICVF_INTR_ID_RBDR 16
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#define NICVF_INTR_ID_MISC 18
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#define NICVF_INTR_ID_QS_ERR 19
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#define RBDR_SIZE0 0ULL /* 8K entries */
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#define RBDR_SIZE1 1ULL /* 16K entries */
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#define RBDR_SIZE2 2ULL /* 32K entries */
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#define RBDR_SIZE3 3ULL /* 64K entries */
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#define RBDR_SIZE4 4ULL /* 126K entries */
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#define RBDR_SIZE5 5ULL /* 256K entries */
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#define RBDR_SIZE6 6ULL /* 512K entries */
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#define SND_QUEUE_SIZE0 0ULL /* 1K entries */
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#define SND_QUEUE_SIZE1 1ULL /* 2K entries */
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#define SND_QUEUE_SIZE2 2ULL /* 4K entries */
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#define SND_QUEUE_SIZE3 3ULL /* 8K entries */
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#define SND_QUEUE_SIZE4 4ULL /* 16K entries */
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#define SND_QUEUE_SIZE5 5ULL /* 32K entries */
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#define SND_QUEUE_SIZE6 6ULL /* 64K entries */
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#define CMP_QUEUE_SIZE0 0ULL /* 1K entries */
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#define CMP_QUEUE_SIZE1 1ULL /* 2K entries */
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#define CMP_QUEUE_SIZE2 2ULL /* 4K entries */
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#define CMP_QUEUE_SIZE3 3ULL /* 8K entries */
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#define CMP_QUEUE_SIZE4 4ULL /* 16K entries */
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#define CMP_QUEUE_SIZE5 5ULL /* 32K entries */
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#define CMP_QUEUE_SIZE6 6ULL /* 64K entries */
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/* Default queue count per QS, its lengths and threshold values */
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#define RBDR_CNT 1
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#define RCV_QUEUE_CNT 1
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#define SND_QUEUE_CNT 1
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#define CMP_QUEUE_CNT 1 /* Max of RCV and SND qcount */
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#define SND_QSIZE SND_QUEUE_SIZE0
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#define SND_QUEUE_LEN BIT_ULL((SND_QSIZE + 10))
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#define SND_QUEUE_THRESH 2ULL
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#define MIN_SQ_DESC_PER_PKT_XMIT 2
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#define MAX_CQE_PER_PKT_XMIT 2
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#define CMP_QSIZE CMP_QUEUE_SIZE0
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#define CMP_QUEUE_LEN BIT_ULL((CMP_QSIZE + 10))
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#define CMP_QUEUE_CQE_THRESH 0
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#define CMP_QUEUE_TIMER_THRESH 1 /* 1 ms */
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#define RBDR_SIZE RBDR_SIZE0
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#define RCV_BUF_COUNT BIT_ULL((RBDR_SIZE + 13))
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#define RBDR_THRESH (RCV_BUF_COUNT / 2)
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#define DMA_BUFFER_LEN 2048 /* In multiples of 128bytes */
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#define RCV_FRAG_LEN DMA_BUFFER_LEN
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#define MAX_CQES_FOR_TX ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) *\
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MAX_CQE_PER_PKT_XMIT)
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#define RQ_CQ_DROP ((CMP_QUEUE_LEN - MAX_CQES_FOR_TX) / 256)
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/* Descriptor size */
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#define SND_QUEUE_DESC_SIZE 16 /* 128 bits */
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#define CMP_QUEUE_DESC_SIZE 512
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/* Buffer / descriptor alignments */
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#define NICVF_RCV_BUF_ALIGN 7
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#define NICVF_RCV_BUF_ALIGN_BYTES BIT_ULL(NICVF_RCV_BUF_ALIGN)
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#define NICVF_CQ_BASE_ALIGN_BYTES 512 /* 9 bits */
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#define NICVF_SQ_BASE_ALIGN_BYTES 128 /* 7 bits */
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#define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES) ALIGN(ADDR, ALIGN_BYTES)
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/* Queue enable/disable */
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#define NICVF_SQ_EN BIT_ULL(19)
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/* Queue reset */
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#define NICVF_CQ_RESET BIT_ULL(41)
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#define NICVF_SQ_RESET BIT_ULL(17)
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#define NICVF_RBDR_RESET BIT_ULL(43)
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enum CQ_RX_ERRLVL_E {
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CQ_ERRLVL_MAC,
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CQ_ERRLVL_L2,
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CQ_ERRLVL_L3,
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CQ_ERRLVL_L4,
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};
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enum CQ_RX_ERROP_E {
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CQ_RX_ERROP_RE_NONE = 0x0,
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CQ_RX_ERROP_RE_PARTIAL = 0x1,
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CQ_RX_ERROP_RE_JABBER = 0x2,
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CQ_RX_ERROP_RE_FCS = 0x7,
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CQ_RX_ERROP_RE_TERMINATE = 0x9,
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CQ_RX_ERROP_RE_RX_CTL = 0xb,
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CQ_RX_ERROP_PREL2_ERR = 0x1f,
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CQ_RX_ERROP_L2_FRAGMENT = 0x20,
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CQ_RX_ERROP_L2_OVERRUN = 0x21,
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CQ_RX_ERROP_L2_PFCS = 0x22,
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CQ_RX_ERROP_L2_PUNY = 0x23,
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CQ_RX_ERROP_L2_MAL = 0x24,
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CQ_RX_ERROP_L2_OVERSIZE = 0x25,
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CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
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CQ_RX_ERROP_L2_LENMISM = 0x27,
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CQ_RX_ERROP_L2_PCLP = 0x28,
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CQ_RX_ERROP_IP_NOT = 0x41,
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CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
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CQ_RX_ERROP_IP_MAL = 0x43,
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CQ_RX_ERROP_IP_MALD = 0x44,
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CQ_RX_ERROP_IP_HOP = 0x45,
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CQ_RX_ERROP_L3_ICRC = 0x46,
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CQ_RX_ERROP_L3_PCLP = 0x47,
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CQ_RX_ERROP_L4_MAL = 0x61,
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CQ_RX_ERROP_L4_CHK = 0x62,
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CQ_RX_ERROP_UDP_LEN = 0x63,
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CQ_RX_ERROP_L4_PORT = 0x64,
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CQ_RX_ERROP_TCP_FLAG = 0x65,
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CQ_RX_ERROP_TCP_OFFSET = 0x66,
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CQ_RX_ERROP_L4_PCLP = 0x67,
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CQ_RX_ERROP_RBDR_TRUNC = 0x70,
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};
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enum CQ_TX_ERROP_E {
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CQ_TX_ERROP_GOOD = 0x0,
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CQ_TX_ERROP_DESC_FAULT = 0x10,
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CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
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CQ_TX_ERROP_SUBDC_ERR = 0x12,
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CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
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CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
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CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
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CQ_TX_ERROP_LOCK_VIOL = 0x83,
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CQ_TX_ERROP_DATA_FAULT = 0x84,
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CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
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CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
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CQ_TX_ERROP_MEM_FAULT = 0x87,
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CQ_TX_ERROP_CK_OVERLAP = 0x88,
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CQ_TX_ERROP_CK_OFLOW = 0x89,
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CQ_TX_ERROP_ENUM_LAST = 0x8a,
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};
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struct cmp_queue_stats {
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struct rx_stats {
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struct {
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u64 mac_errs;
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u64 l2_errs;
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u64 l3_errs;
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u64 l4_errs;
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} errlvl;
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struct {
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u64 good;
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u64 partial_pkts;
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u64 jabber_errs;
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u64 fcs_errs;
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u64 terminate_errs;
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u64 bgx_rx_errs;
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u64 prel2_errs;
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u64 l2_frags;
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u64 l2_overruns;
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u64 l2_pfcs;
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u64 l2_puny;
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u64 l2_hdr_malformed;
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u64 l2_oversize;
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u64 l2_undersize;
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u64 l2_len_mismatch;
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u64 l2_pclp;
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u64 non_ip;
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u64 ip_csum_err;
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u64 ip_hdr_malformed;
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u64 ip_payload_malformed;
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u64 ip_hop_errs;
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u64 l3_icrc_errs;
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u64 l3_pclp;
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u64 l4_malformed;
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u64 l4_csum_errs;
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u64 udp_len_err;
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u64 bad_l4_port;
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u64 bad_tcp_flag;
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u64 tcp_offset_errs;
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u64 l4_pclp;
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u64 pkt_truncated;
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} errop;
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} rx;
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struct tx_stats {
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u64 good;
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u64 desc_fault;
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u64 hdr_cons_err;
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u64 subdesc_err;
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u64 imm_size_oflow;
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u64 data_seq_err;
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u64 mem_seq_err;
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u64 lock_viol;
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u64 data_fault;
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u64 tstmp_conflict;
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u64 tstmp_timeout;
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u64 mem_fault;
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u64 csum_overlap;
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u64 csum_overflow;
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} tx;
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};
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enum RQ_SQ_STATS {
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RQ_SQ_STATS_OCTS,
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RQ_SQ_STATS_PKTS,
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};
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struct rx_tx_queue_stats {
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u64 bytes;
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u64 pkts;
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};
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struct q_desc_mem {
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uintptr_t dma;
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u64 size;
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u16 q_len;
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uintptr_t phys_base;
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void *base;
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void *unalign_base;
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bool allocated;
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};
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struct rbdr {
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bool enable;
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u32 dma_size;
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u32 thresh; /* Threshold level for interrupt */
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void *desc;
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u32 head;
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u32 tail;
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struct q_desc_mem dmem;
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uintptr_t buf_mem;
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uintptr_t buffers;
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};
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struct rcv_queue {
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bool enable;
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struct rbdr *rbdr_start;
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struct rbdr *rbdr_cont;
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bool en_tcp_reassembly;
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u8 cq_qs; /* CQ's QS to which this RQ is assigned */
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u8 cq_idx; /* CQ index (0 to 7) in the QS */
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u8 cont_rbdr_qs; /* Continue buffer ptrs - QS num */
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u8 cont_qs_rbdr_idx; /* RBDR idx in the cont QS */
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u8 start_rbdr_qs; /* First buffer ptrs - QS num */
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u8 start_qs_rbdr_idx; /* RBDR idx in the above QS */
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u8 caching;
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struct rx_tx_queue_stats stats;
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};
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struct cmp_queue {
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bool enable;
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u16 intr_timer_thresh;
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u16 thresh;
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void *desc;
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struct q_desc_mem dmem;
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struct cmp_queue_stats stats;
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};
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struct snd_queue {
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bool enable;
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u8 cq_qs; /* CQ's QS to which this SQ is pointing */
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u8 cq_idx; /* CQ index (0 to 7) in the above QS */
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u16 thresh;
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u32 free_cnt;
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u32 head;
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u32 tail;
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u64 *skbuff;
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void *desc;
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struct q_desc_mem dmem;
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struct rx_tx_queue_stats stats;
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};
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struct queue_set {
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bool enable;
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bool be_en;
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u8 vnic_id;
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u8 rq_cnt;
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u8 cq_cnt;
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u64 cq_len;
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u8 sq_cnt;
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u64 sq_len;
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u8 rbdr_cnt;
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u64 rbdr_len;
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struct rcv_queue rq[MAX_RCV_QUEUES_PER_QS];
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struct cmp_queue cq[MAX_CMP_QUEUES_PER_QS];
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struct snd_queue sq[MAX_SND_QUEUES_PER_QS];
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struct rbdr rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS];
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};
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#define GET_RBDR_DESC(RING, idx)\
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(&(((struct rbdr_entry_t *)((RING)->desc))[idx]))
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#define GET_SQ_DESC(RING, idx)\
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(&(((struct sq_hdr_subdesc *)((RING)->desc))[idx]))
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#define GET_CQ_DESC(RING, idx)\
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(&(((union cq_desc_t *)((RING)->desc))[idx]))
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/* CQ status bits */
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#define CQ_WR_FULL BIT(26)
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#define CQ_WR_DISABLE BIT(25)
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#define CQ_WR_FAULT BIT(24)
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#define CQ_CQE_COUNT (0xFFFF << 0)
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#define CQ_ERR_MASK (CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT)
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int nicvf_set_qset_resources(struct nicvf *nic);
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int nicvf_config_data_transfer(struct nicvf *nic, bool enable);
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void nicvf_qset_config(struct nicvf *nic, bool enable);
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void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
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int qidx, bool enable);
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void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx);
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void nicvf_sq_disable(struct nicvf *nic, int qidx);
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void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt);
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void nicvf_sq_free_used_descs(struct udevice *dev,
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struct snd_queue *sq, int qidx);
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int nicvf_sq_append_pkt(struct nicvf *nic, void *pkt, size_t pkt_len);
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void *nicvf_get_rcv_pkt(struct nicvf *nic, void *cq_desc, size_t *pkt_len);
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void nicvf_refill_rbdr(struct nicvf *nic);
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void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx);
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void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx);
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void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx);
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int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx);
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/* Register access APIs */
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void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val);
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u64 nicvf_reg_read(struct nicvf *nic, u64 offset);
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void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val);
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u64 nicvf_qset_reg_read(struct nicvf *nic, u64 offset);
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void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
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u64 qidx, u64 val);
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u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx);
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/* Stats */
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void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx);
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void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx);
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int nicvf_check_cqe_rx_errs(struct nicvf *nic,
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struct cmp_queue *cq, void *cq_desc);
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int nicvf_check_cqe_tx_errs(struct nicvf *nic,
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struct cmp_queue *cq, void *cq_desc);
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#endif /* NICVF_QUEUES_H */
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