95 lines
1.8 KiB
C
95 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RZ/A1 R7S72100 OSTM Timer driver
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*
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <malloc.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <clk.h>
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#include <timer.h>
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#include <linux/bitops.h>
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#define OSTM_CMP 0x00
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#define OSTM_CNT 0x04
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#define OSTM_TE 0x10
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#define OSTM_TS 0x14
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#define OSTM_TT 0x18
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#define OSTM_CTL 0x20
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#define OSTM_CTL_D BIT(1)
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DECLARE_GLOBAL_DATA_PTR;
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struct ostm_priv {
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fdt_addr_t regs;
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};
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static u64 ostm_get_count(struct udevice *dev)
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{
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struct ostm_priv *priv = dev_get_priv(dev);
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return timer_conv_64(readl(priv->regs + OSTM_CNT));
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}
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static int ostm_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct ostm_priv *priv = dev_get_priv(dev);
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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uc_priv->clock_rate = clk_get_rate(&clk);
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clk_free(&clk);
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#else
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uc_priv->clock_rate = get_board_sys_clk() / 2;
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#endif
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readb(priv->regs + OSTM_CTL);
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writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
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setbits_8(priv->regs + OSTM_TT, BIT(0));
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writel(0xffffffff, priv->regs + OSTM_CMP);
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setbits_8(priv->regs + OSTM_TS, BIT(0));
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return 0;
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}
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static int ostm_of_to_plat(struct udevice *dev)
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{
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struct ostm_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr(dev);
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return 0;
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}
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static const struct timer_ops ostm_ops = {
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.get_count = ostm_get_count,
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};
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static const struct udevice_id ostm_ids[] = {
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{ .compatible = "renesas,ostm" },
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{}
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};
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U_BOOT_DRIVER(ostm_timer) = {
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.name = "ostm-timer",
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.id = UCLASS_TIMER,
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.ops = &ostm_ops,
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.probe = ostm_probe,
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.of_match = ostm_ids,
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.of_to_plat = ostm_of_to_plat,
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.priv_auto = sizeof(struct ostm_priv),
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};
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