77 lines
1.3 KiB
C
77 lines
1.3 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TOPOLOGY_DEF_H
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#define _DDR3_TOPOLOGY_DEF_H
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/* TOPOLOGY */
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enum hws_speed_bin {
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SPEED_BIN_DDR_800D,
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SPEED_BIN_DDR_800E,
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SPEED_BIN_DDR_1066E,
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SPEED_BIN_DDR_1066F,
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SPEED_BIN_DDR_1066G,
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SPEED_BIN_DDR_1333F,
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SPEED_BIN_DDR_1333G,
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SPEED_BIN_DDR_1333H,
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SPEED_BIN_DDR_1333J,
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SPEED_BIN_DDR_1600G,
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SPEED_BIN_DDR_1600H,
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SPEED_BIN_DDR_1600J,
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SPEED_BIN_DDR_1600K,
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SPEED_BIN_DDR_1866J,
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SPEED_BIN_DDR_1866K,
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SPEED_BIN_DDR_1866L,
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SPEED_BIN_DDR_1866M,
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SPEED_BIN_DDR_2133K,
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SPEED_BIN_DDR_2133L,
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SPEED_BIN_DDR_2133M,
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SPEED_BIN_DDR_2133N,
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SPEED_BIN_DDR_1333H_EXT,
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SPEED_BIN_DDR_1600K_EXT,
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SPEED_BIN_DDR_1866M_EXT
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};
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enum hws_ddr_freq {
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DDR_FREQ_LOW_FREQ,
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DDR_FREQ_400,
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DDR_FREQ_533,
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DDR_FREQ_667,
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DDR_FREQ_800,
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DDR_FREQ_933,
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DDR_FREQ_1066,
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DDR_FREQ_311,
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DDR_FREQ_333,
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DDR_FREQ_467,
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DDR_FREQ_850,
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DDR_FREQ_600,
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DDR_FREQ_300,
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DDR_FREQ_900,
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DDR_FREQ_360,
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DDR_FREQ_1000,
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DDR_FREQ_LIMIT
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};
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enum speed_bin_table_elements {
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SPEED_BIN_TRCD,
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SPEED_BIN_TRP,
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SPEED_BIN_TRAS,
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SPEED_BIN_TRC,
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SPEED_BIN_TRRD1K,
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SPEED_BIN_TRRD2K,
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SPEED_BIN_TPD,
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SPEED_BIN_TFAW1K,
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SPEED_BIN_TFAW2K,
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SPEED_BIN_TWTR,
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SPEED_BIN_TRTP,
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SPEED_BIN_TWR,
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SPEED_BIN_TMOD
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};
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#endif /* _DDR3_TOPOLOGY_DEF_H */
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