667 lines
17 KiB
C
667 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013 - 2015 Xilinx, Inc.
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*
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* Xilinx Zynq SD Host Controller Interface
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/delay.h>
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#include "mmc_private.h"
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#include <log.h>
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <zynqmp_tap_delay.h>
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#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
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#define SDHCI_ARASAN_ITAPDLY_SEL_MASK GENMASK(7, 0)
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#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
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#define SDHCI_ARASAN_OTAPDLY_SEL_MASK GENMASK(5, 0)
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#define SDHCI_ITAPDLY_CHGWIN BIT(9)
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#define SDHCI_ITAPDLY_ENABLE BIT(8)
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#define SDHCI_OTAPDLY_ENABLE BIT(6)
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#define SDHCI_TUNING_LOOP_COUNT 40
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#define MMC_BANK2 0x2
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struct arasan_sdhci_clk_data {
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int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
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int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
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};
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struct arasan_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct arasan_sdhci_priv {
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struct sdhci_host *host;
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struct arasan_sdhci_clk_data clk_data;
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u8 deviceid;
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u8 bank;
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u8 no_1p8;
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};
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#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
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/* Default settings for ZynqMP Clock Phases */
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static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
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0, 183, 54, 0, 0};
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static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
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135, 48, 72, 135, 0};
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/* Default settings for Versal Clock Phases */
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static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
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0, 0, 162, 90, 0, 0};
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static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
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90, 36, 60, 90, 0};
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static const u8 mode2timing[] = {
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[MMC_LEGACY] = MMC_TIMING_LEGACY,
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[MMC_HS] = MMC_TIMING_MMC_HS,
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[SD_HS] = MMC_TIMING_SD_HS,
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[MMC_HS_52] = MMC_TIMING_UHS_SDR50,
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[MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
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[UHS_SDR12] = MMC_TIMING_UHS_SDR12,
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[UHS_SDR25] = MMC_TIMING_UHS_SDR25,
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[UHS_SDR50] = MMC_TIMING_UHS_SDR50,
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[UHS_DDR50] = MMC_TIMING_UHS_DDR50,
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[UHS_SDR104] = MMC_TIMING_UHS_SDR104,
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[MMC_HS_200] = MMC_TIMING_MMC_HS200,
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};
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static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
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{
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u16 clk;
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unsigned long timeout;
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= ~(SDHCI_CLOCK_CARD_EN);
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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/* Issue DLL Reset */
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zynqmp_dll_reset(deviceid);
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/* Wait max 20 ms */
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timeout = 100;
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (timeout == 0) {
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dev_err(mmc_dev(host->mmc),
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": Internal clock never stabilised.\n");
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return;
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}
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timeout--;
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udelay(1000);
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}
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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}
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static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
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{
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struct mmc_cmd cmd;
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struct mmc_data data;
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u32 ctrl;
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struct sdhci_host *host;
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struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
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char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
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u8 deviceid;
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debug("%s\n", __func__);
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host = priv->host;
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deviceid = priv->deviceid;
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl |= SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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mdelay(1);
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arasan_zynqmp_dll_reset(host, deviceid);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
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do {
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cmd.cmdidx = opcode;
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cmd.resp_type = MMC_RSP_R1;
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cmd.cmdarg = 0;
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data.blocksize = 64;
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data.blocks = 1;
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data.flags = MMC_DATA_READ;
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if (tuning_loop_counter-- == 0)
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break;
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if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
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mmc->bus_width == 8)
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data.blocksize = 128;
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sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
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data.blocksize),
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SDHCI_BLOCK_SIZE);
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sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
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sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
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mmc_send_cmd(mmc, &cmd, NULL);
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
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udelay(1);
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} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
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if (tuning_loop_counter < 0) {
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ctrl &= ~SDHCI_CTRL_TUNED_CLK;
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sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
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}
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if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
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printf("%s:Tuning failed\n", __func__);
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return -1;
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}
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udelay(1);
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arasan_zynqmp_dll_reset(host, deviceid);
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/* Enable only interrupts served by the SD controller */
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sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
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SDHCI_INT_ENABLE);
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/* Mask all sdhci interrupt sources */
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sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
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return 0;
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}
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/**
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* sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
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*
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* @host: Pointer to the sdhci_host structure.
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* @degrees: The clock phase shift between 0 - 359.
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* Return: 0
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*
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* Set the SD Output Clock Tap Delays for Output path
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*/
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static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
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int degrees)
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{
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struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
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struct mmc *mmc = (struct mmc *)host->mmc;
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u8 tap_delay, tap_max = 0;
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int timing = mode2timing[mmc->selected_mode];
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/*
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* This is applicable for SDHCI_SPEC_300 and above
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* ZynqMP does not set phase for <=25MHz clock.
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* If degrees is zero, no need to do anything.
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*/
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if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
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return 0;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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/* For 50MHz clock, 30 Taps are available */
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tap_max = 30;
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break;
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case MMC_TIMING_UHS_SDR50:
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/* For 100MHz clock, 15 Taps are available */
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tap_max = 15;
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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/* For 200MHz clock, 8 Taps are available */
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tap_max = 8;
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default:
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break;
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}
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tap_delay = (degrees * tap_max) / 360;
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/* Limit output tap_delay value to 6 bits */
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tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
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arasan_zynqmp_set_out_tapdelay(priv->deviceid, tap_delay);
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return 0;
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}
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/**
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* sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
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*
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* @host: Pointer to the sdhci_host structure.
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* @degrees: The clock phase shift between 0 - 359.
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* Return: 0
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*
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* Set the SD Input Clock Tap Delays for Input path
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*/
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static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
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int degrees)
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{
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struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
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struct mmc *mmc = (struct mmc *)host->mmc;
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u8 tap_delay, tap_max = 0;
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int timing = mode2timing[mmc->selected_mode];
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/*
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* This is applicable for SDHCI_SPEC_300 and above
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* ZynqMP does not set phase for <=25MHz clock.
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* If degrees is zero, no need to do anything.
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*/
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if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
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return 0;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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/* For 50MHz clock, 120 Taps are available */
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tap_max = 120;
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break;
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case MMC_TIMING_UHS_SDR50:
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/* For 100MHz clock, 60 Taps are available */
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tap_max = 60;
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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/* For 200MHz clock, 30 Taps are available */
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tap_max = 30;
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default:
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break;
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}
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tap_delay = (degrees * tap_max) / 360;
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/* Limit input tap_delay value to 8 bits */
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tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
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arasan_zynqmp_set_in_tapdelay(priv->deviceid, tap_delay);
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return 0;
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}
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/**
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* sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
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*
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* @host: Pointer to the sdhci_host structure.
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* @degrees: The clock phase shift between 0 - 359.
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* Return: 0
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*
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* Set the SD Output Clock Tap Delays for Output path
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*/
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static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
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int degrees)
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{
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struct mmc *mmc = (struct mmc *)host->mmc;
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u8 tap_delay, tap_max = 0;
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int timing = mode2timing[mmc->selected_mode];
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u32 regval;
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/*
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* This is applicable for SDHCI_SPEC_300 and above
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* Versal does not set phase for <=25MHz clock.
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* If degrees is zero, no need to do anything.
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*/
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if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
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return 0;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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/* For 50MHz clock, 30 Taps are available */
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tap_max = 30;
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break;
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case MMC_TIMING_UHS_SDR50:
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/* For 100MHz clock, 15 Taps are available */
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tap_max = 15;
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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/* For 200MHz clock, 8 Taps are available */
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tap_max = 8;
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default:
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break;
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}
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tap_delay = (degrees * tap_max) / 360;
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/* Limit output tap_delay value to 6 bits */
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tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
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/* Set the Clock Phase */
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regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
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regval |= SDHCI_OTAPDLY_ENABLE;
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sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
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regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
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regval |= tap_delay;
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sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
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return 0;
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}
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/**
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* sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
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*
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* @host: Pointer to the sdhci_host structure.
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* @degrees: The clock phase shift between 0 - 359.
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* Return: 0
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*
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* Set the SD Input Clock Tap Delays for Input path
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*/
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static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
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int degrees)
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{
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struct mmc *mmc = (struct mmc *)host->mmc;
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u8 tap_delay, tap_max = 0;
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int timing = mode2timing[mmc->selected_mode];
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u32 regval;
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/*
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* This is applicable for SDHCI_SPEC_300 and above
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* Versal does not set phase for <=25MHz clock.
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* If degrees is zero, no need to do anything.
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*/
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if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
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return 0;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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/* For 50MHz clock, 120 Taps are available */
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tap_max = 120;
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break;
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case MMC_TIMING_UHS_SDR50:
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/* For 100MHz clock, 60 Taps are available */
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tap_max = 60;
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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/* For 200MHz clock, 30 Taps are available */
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tap_max = 30;
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default:
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break;
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}
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tap_delay = (degrees * tap_max) / 360;
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/* Limit input tap_delay value to 8 bits */
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tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
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/* Set the Clock Phase */
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regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
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regval |= SDHCI_ITAPDLY_CHGWIN;
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sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
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regval |= SDHCI_ITAPDLY_ENABLE;
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sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
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regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
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regval |= tap_delay;
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sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
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regval &= ~SDHCI_ITAPDLY_CHGWIN;
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sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
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return 0;
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}
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static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
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{
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struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
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struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
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struct mmc *mmc = (struct mmc *)host->mmc;
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struct udevice *dev = mmc->dev;
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u8 timing = mode2timing[mmc->selected_mode];
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u32 iclk_phase = clk_data->clk_phase_in[timing];
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u32 oclk_phase = clk_data->clk_phase_out[timing];
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dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
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if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
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device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
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sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
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sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
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} else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
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device_is_compatible(dev, "xlnx,versal-8.9a")) {
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sdhci_versal_sampleclk_set_phase(host, iclk_phase);
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sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
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}
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}
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static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
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const char *prop)
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{
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struct arasan_sdhci_priv *priv = dev_get_priv(dev);
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struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
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u32 clk_phase[2] = {0};
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/*
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* Read Tap Delay values from DT, if the DT does not contain the
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* Tap Values then use the pre-defined values
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*/
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if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
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dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
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prop, clk_data->clk_phase_in[timing],
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clk_data->clk_phase_out[timing]);
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return;
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}
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|
|
|
/* The values read are Input and Output Clock Delays in order */
|
|
clk_data->clk_phase_in[timing] = clk_phase[0];
|
|
clk_data->clk_phase_out[timing] = clk_phase[1];
|
|
}
|
|
|
|
/**
|
|
* arasan_dt_parse_clk_phases - Read Tap Delay values from DT
|
|
*
|
|
* @dev: Pointer to our struct udevice.
|
|
*
|
|
* Called at initialization to parse the values of Tap Delays.
|
|
*/
|
|
static void arasan_dt_parse_clk_phases(struct udevice *dev)
|
|
{
|
|
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
|
|
struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
|
|
int i;
|
|
|
|
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
|
|
device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
|
|
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
|
|
clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
|
|
clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
|
|
}
|
|
|
|
if (priv->bank == MMC_BANK2) {
|
|
clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
|
|
clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
|
|
}
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
|
|
device_is_compatible(dev, "xlnx,versal-8.9a")) {
|
|
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
|
|
clk_data->clk_phase_in[i] = versal_iclk_phases[i];
|
|
clk_data->clk_phase_out[i] = versal_oclk_phases[i];
|
|
}
|
|
}
|
|
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
|
|
"clk-phase-legacy");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
|
|
"clk-phase-mmc-hs");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
|
|
"clk-phase-sd-hs");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
|
|
"clk-phase-uhs-sdr12");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
|
|
"clk-phase-uhs-sdr25");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
|
|
"clk-phase-uhs-sdr50");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
|
|
"clk-phase-uhs-sdr104");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
|
|
"clk-phase-uhs-ddr50");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
|
|
"clk-phase-mmc-ddr52");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
|
|
"clk-phase-mmc-hs200");
|
|
arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
|
|
"clk-phase-mmc-hs400");
|
|
}
|
|
|
|
static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
|
|
{
|
|
struct mmc *mmc = (struct mmc *)host->mmc;
|
|
u32 reg;
|
|
|
|
if (!IS_SD(mmc))
|
|
return;
|
|
|
|
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
|
|
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
reg |= SDHCI_CTRL_VDD_180;
|
|
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
|
|
}
|
|
|
|
if (mmc->selected_mode > SD_HS &&
|
|
mmc->selected_mode <= MMC_HS_200)
|
|
sdhci_set_uhs_timing(host);
|
|
}
|
|
|
|
static const struct sdhci_ops arasan_ops = {
|
|
.platform_execute_tuning = &arasan_sdhci_execute_tuning,
|
|
.set_delay = &arasan_sdhci_set_tapdelay,
|
|
.set_control_reg = &arasan_sdhci_set_control_reg,
|
|
};
|
|
#endif
|
|
|
|
static int arasan_sdhci_probe(struct udevice *dev)
|
|
{
|
|
struct arasan_sdhci_plat *plat = dev_get_plat(dev);
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
|
|
struct sdhci_host *host;
|
|
struct clk clk;
|
|
unsigned long clock;
|
|
int ret;
|
|
|
|
host = priv->host;
|
|
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get clock\n");
|
|
return ret;
|
|
}
|
|
|
|
clock = clk_get_rate(&clk);
|
|
if (IS_ERR_VALUE(clock)) {
|
|
dev_err(dev, "failed to get rate\n");
|
|
return clock;
|
|
}
|
|
|
|
debug("%s: CLK %ld\n", __func__, clock);
|
|
|
|
ret = clk_enable(&clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
|
|
SDHCI_QUIRK_BROKEN_R1B;
|
|
|
|
#ifdef CONFIG_ZYNQ_HISPD_BROKEN
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
|
|
#endif
|
|
|
|
if (priv->no_1p8)
|
|
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
|
|
|
|
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
|
|
|
|
ret = mmc_of_parse(dev, &plat->cfg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
host->max_clk = clock;
|
|
|
|
host->mmc = &plat->mmc;
|
|
host->mmc->dev = dev;
|
|
host->mmc->priv = host;
|
|
|
|
ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
|
|
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
|
|
if (ret)
|
|
return ret;
|
|
upriv->mmc = host->mmc;
|
|
|
|
return sdhci_probe(dev);
|
|
}
|
|
|
|
static int arasan_sdhci_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->host = calloc(1, sizeof(struct sdhci_host));
|
|
if (!priv->host)
|
|
return -1;
|
|
|
|
priv->host->name = dev->name;
|
|
|
|
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
|
|
priv->host->ops = &arasan_ops;
|
|
arasan_dt_parse_clk_phases(dev);
|
|
#endif
|
|
|
|
priv->host->ioaddr = (void *)dev_read_addr(dev);
|
|
if (IS_ERR(priv->host->ioaddr))
|
|
return PTR_ERR(priv->host->ioaddr);
|
|
|
|
priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
|
|
priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
|
|
priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int arasan_sdhci_bind(struct udevice *dev)
|
|
{
|
|
struct arasan_sdhci_plat *plat = dev_get_plat(dev);
|
|
|
|
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
static const struct udevice_id arasan_sdhci_ids[] = {
|
|
{ .compatible = "arasan,sdhci-8.9a" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(arasan_sdhci_drv) = {
|
|
.name = "arasan_sdhci",
|
|
.id = UCLASS_MMC,
|
|
.of_match = arasan_sdhci_ids,
|
|
.of_to_plat = arasan_sdhci_of_to_plat,
|
|
.ops = &sdhci_ops,
|
|
.bind = arasan_sdhci_bind,
|
|
.probe = arasan_sdhci_probe,
|
|
.priv_auto = sizeof(struct arasan_sdhci_priv),
|
|
.plat_auto = sizeof(struct arasan_sdhci_plat),
|
|
};
|