196 lines
5.4 KiB
C
196 lines
5.4 KiB
C
/*
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* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
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* Copyright (C) 2007-2009 DENX Software Engineering
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Derived from the MPC83xx code.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/mpc512x.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Set up the memory map, initialize registers,
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*/
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void cpu_init_f (volatile immap_t * im)
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{
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u32 ips_div;
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/* Local Window and chip select configuration */
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#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
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out_be32(&im->sysconf.lpcs0aw,
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CSAW_START(CONFIG_SYS_CS0_START) |
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CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
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sync_law(&im->sysconf.lpcs0aw);
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#endif
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#if defined(CONFIG_SYS_CS0_CFG)
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out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
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#endif
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#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
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out_be32(&im->sysconf.lpcs1aw,
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CSAW_START(CONFIG_SYS_CS1_START) |
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CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
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sync_law(&im->sysconf.lpcs1aw);
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#endif
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#if defined(CONFIG_SYS_CS1_CFG)
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out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
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#endif
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#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
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out_be32(&im->sysconf.lpcs2aw,
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CSAW_START(CONFIG_SYS_CS2_START) |
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CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
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sync_law(&im->sysconf.lpcs2aw);
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#endif
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#if defined(CONFIG_SYS_CS2_CFG)
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out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
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#endif
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#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
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out_be32(&im->sysconf.lpcs3aw,
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CSAW_START(CONFIG_SYS_CS3_START) |
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CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
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sync_law(&im->sysconf.lpcs3aw);
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#endif
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#if defined(CONFIG_SYS_CS3_CFG)
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out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
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#endif
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#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
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out_be32(&im->sysconf.lpcs4aw,
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CSAW_START(CONFIG_SYS_CS4_START) |
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CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
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sync_law(&im->sysconf.lpcs4aw);
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#endif
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#if defined(CONFIG_SYS_CS4_CFG)
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out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
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#endif
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#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
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out_be32(&im->sysconf.lpcs5aw,
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CSAW_START(CONFIG_SYS_CS5_START) |
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CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
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sync_law(&im->sysconf.lpcs5aw);
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#endif
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#if defined(CONFIG_SYS_CS5_CFG)
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out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
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#endif
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#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
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out_be32(&im->sysconf.lpcs6aw,
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CSAW_START(CONFIG_SYS_CS6_START) |
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CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
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sync_law(&im->sysconf.lpcs6aw);
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#endif
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#if defined(CONFIG_SYS_CS6_CFG)
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out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
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#endif
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#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
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out_be32(&im->sysconf.lpcs7aw,
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CSAW_START(CONFIG_SYS_CS7_START) |
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CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
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sync_law(&im->sysconf.lpcs7aw);
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#endif
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#if defined(CONFIG_SYS_CS7_CFG)
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out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
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#endif
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#if defined CONFIG_SYS_CS_ALETIMING
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if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
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out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
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#endif
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#if defined CONFIG_SYS_CS_BURST
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out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
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#endif
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#if defined CONFIG_SYS_CS_DEADCYCLE
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out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
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#endif
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#if defined CONFIG_SYS_CS_HOLDCYCLE
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out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
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#endif
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/* system performance tweaking */
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#ifdef CONFIG_SYS_ACR_PIPE_DEP
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/* Arbiter pipeline depth */
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out_be32(&im->arbiter.acr,
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(im->arbiter.acr & ~ACR_PIPE_DEP) |
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(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
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);
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#endif
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#ifdef CONFIG_SYS_ACR_RPTCNT
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/* Arbiter repeat count */
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out_be32(im->arbiter.acr,
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(im->arbiter.acr & ~(ACR_RPTCNT)) |
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(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
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);
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#endif
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/* RSR - Reset Status Register - clear all status */
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gd->arch.reset_status = im->reset.rsr;
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out_be32(&im->reset.rsr, ~RSR_RES);
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/*
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* RMR - Reset Mode Register - enable checkstop reset
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*/
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out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
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/* Set IPS-CSB divider: IPS = 1/2 CSB */
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ips_div = in_be32(&im->clk.scfr[0]);
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ips_div &= ~(SCFR1_IPS_DIV_MASK);
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ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
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out_be32(&im->clk.scfr[0], ips_div);
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#ifdef SCFR1_LPC_DIV
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clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
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SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
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#endif
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#ifdef SCFR1_NFC_DIV
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clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
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SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
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#endif
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#ifdef SCFR1_DIU_DIV
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clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
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SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
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#endif
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/*
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* Enable Time Base/Decrementer
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*
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* NOTICE: TB needs to be enabled as early as possible in order to
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* have udelay() working; if not enabled, usually leads to a hang, like
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* during FLASH chip identification etc.
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*/
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setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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}
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int cpu_init_r (void)
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{
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return 0;
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}
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