805 lines
28 KiB
C
805 lines
28 KiB
C
/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_MPC85xx_CONFIG_H_
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#define _ASM_MPC85xx_CONFIG_H_
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/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
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#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
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#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
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#endif
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/*
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* This macro should be removed when we no longer care about backwards
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* compatibility with older operating systems.
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*/
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#define CONFIG_PPC_SPINTABLE_COMPATIBLE
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#define FSL_DDR_VER_4_7 47
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#define FSL_DDR_VER_5_0 50
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/* IP endianness */
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#define CONFIG_SYS_FSL_IFC_BE
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/* Number of TLB CAM entries we have on FSL Book-E chips */
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#if defined(CONFIG_E500MC)
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#define CONFIG_SYS_NUM_TLBCAMS 64
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#elif defined(CONFIG_E500)
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#define CONFIG_SYS_NUM_TLBCAMS 16
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#endif
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#if defined(CONFIG_MPC8536)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_MPC8540)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8541)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8544)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_MPC8548)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
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#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
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#elif defined(CONFIG_MPC8555)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8560)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8568)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x10000UL
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#define MAX_QE_RISC 2
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_MPC8569)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x20000UL
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#define MAX_QE_RISC 4
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#define QE_NUM_OF_SNUM 46
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_MPC8572)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_DDR_115
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#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1010)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
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#define CONFIG_ESDHC_HC_BLK_ADDR
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/* P1011 is single core version of P1020 */
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#elif defined(CONFIG_P1011)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P1012 is single core version of P1021 */
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#elif defined(CONFIG_P1012)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P1013 is single core version of P1022 */
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#elif defined(CONFIG_P1013)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_FSL_SATA_ERRATUM_A001
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1014)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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/* P1017 is single core version of P1023 */
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#elif defined(CONFIG_P1017)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 2
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_QMAN_NUM_PORTALS 3
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#define CONFIG_SYS_BMAN_NUM_PORTALS 3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1020)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#elif defined(CONFIG_P1021)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#elif defined(CONFIG_P1022)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_FSL_SATA_ERRATUM_A001
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1023)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 2
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_QMAN_NUM_PORTALS 3
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#define CONFIG_SYS_BMAN_NUM_PORTALS 3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
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/* P1024 is lower end variant of P1020 */
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#elif defined(CONFIG_P1024)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P1025 is lower end variant of P1021 */
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#elif defined(CONFIG_P1025)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P2010 is single core version of P2020 */
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#elif defined(CONFIG_P2010)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P2020)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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#define CONFIG_SYS_FSL_ERRATUM_USB14
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#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
|
|
|
#elif defined(CONFIG_PPC_P3041)
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_MAX_CPUS 4
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
|
|
#define CONFIG_SYS_FSL_ERRATUM_USB14
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
|
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
|
|
|
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_MAX_CPUS 8
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 2
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 4
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
|
|
#define CONFIG_SYS_P4080_ERRATUM_CPU22
|
|
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
#define CONFIG_SYS_FSL_RMU
|
|
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
|
|
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004580
|
|
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
|
|
|
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_MAX_CPUS 2
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
#define CONFIG_SYS_FSL_ERRATUM_USB14
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
|
|
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
|
|
|
#elif defined(CONFIG_PPC_P5040)
|
|
#define CONFIG_SYS_PPC64
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_MAX_CPUS 4
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 2
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 5
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
#define CONFIG_SYS_FSL_ERRATUM_USB14
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004699
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
|
|
|
#elif defined(CONFIG_BSC9131)
|
|
#define CONFIG_MAX_CPUS 1
|
|
#define CONFIG_FSL_SDHC_V2_3
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
|
#define CONFIG_TSECV2
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
|
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
|
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
|
#define CONFIG_NAND_FSL_IFC
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
|
#define CONFIG_ESDHC_HC_BLK_ADDR
|
|
|
|
#elif defined(CONFIG_BSC9132)
|
|
#define CONFIG_MAX_CPUS 2
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
|
#define CONFIG_FSL_SDHC_V2_3
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
|
#define CONFIG_TSECV2
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
|
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
|
|
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
|
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
|
|
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
|
#define CONFIG_NAND_FSL_IFC
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
|
#define CONFIG_ESDHC_HC_BLK_ADDR
|
|
|
|
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
|
|
#define CONFIG_E6500
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
|
#ifdef CONFIG_PPC_T4240
|
|
#define CONFIG_MAX_CPUS 12
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 8
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 2
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 3
|
|
#else
|
|
#define CONFIG_MAX_CPUS 8
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 7
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 7
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
|
#endif
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SRDS_1
|
|
#define CONFIG_SYS_FSL_SRDS_2
|
|
#define CONFIG_SYS_FSL_SRDS_3
|
|
#define CONFIG_SYS_FSL_SRDS_4
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 2
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
#define CONFIG_SYS_PME_CLK 0
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
|
#define CONFIG_SYS_FMAN_V3
|
|
#define CONFIG_SYS_FM1_CLK 3
|
|
#define CONFIG_SYS_FM2_CLK 3
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
#define CONFIG_SYS_FSL_SRIO_LIODN
|
|
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004468
|
|
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006593
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
|
|
|
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
|
|
#define CONFIG_E6500
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SRDS_1
|
|
#define CONFIG_SYS_FSL_SRDS_2
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
|
#define CONFIG_SYS_FM1_CLK 0
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
|
|
#define CONFIG_SYS_FMAN_V3
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006593
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
|
|
#ifdef CONFIG_PPC_B4860
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
|
#define CONFIG_MAX_CPUS 4
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
#define CONFIG_SYS_FSL_SRIO_LIODN
|
|
#else
|
|
#define CONFIG_MAX_CPUS 2
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 0
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
|
#endif
|
|
|
|
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
|
|
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|
#define CONFIG_E5500
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
|
#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
|
|
#define CONFIG_MAX_CPUS 4
|
|
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|
#define CONFIG_MAX_CPUS 2
|
|
#endif
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
|
#define CONFIG_SYS_SDHC_CLOCK 0
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 16
|
|
#define CONFIG_SYS_FSL_SRDS_1
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
#define CONFIG_PME_PLAT_CLK_DIV 2
|
|
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
|
#define CONFIG_SYS_FMAN_V3
|
|
#define CONFIG_FM_PLAT_CLK_DIV 1
|
|
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
|
|
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
|
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
|
|
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
|
#define CONFIG_E6500
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_QMAN_V3
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_PCI_VER_3_X
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#if defined(CONFIG_PPC_T2080)
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#define CONFIG_SYS_NUM_FM1_DTSEC 8
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#define CONFIG_SYS_NUM_FM1_10GEC 4
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#define CONFIG_SYS_FSL_SRDS_2
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#define CONFIG_SYS_FSL_SRIO_LIODN
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#elif defined(CONFIG_PPC_T2081)
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#define CONFIG_SYS_NUM_FM1_DTSEC 6
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#define CONFIG_SYS_NUM_FM1_10GEC 2
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#endif
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_PME_PLAT_CLK_DIV 1
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#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
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#define CONFIG_SYS_FM1_CLK 0
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_FMAN_V3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_ISBC_VER 2
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#elif defined(CONFIG_PPC_C29X)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2_1
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#define CONFIG_SYS_FSL_SEC_COMPAT 6
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#else
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#error Processor type not defined for this platform
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#endif
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#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
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#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
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#endif
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#ifdef CONFIG_E6500
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#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
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#else
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#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
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#endif
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#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
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!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
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!defined(CONFIG_SYS_FSL_DDRC_GEN3)
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#define CONFIG_SYS_FSL_DDRC_GEN3
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#endif
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#endif /* _ASM_MPC85xx_CONFIG_H_ */
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