81 lines
2.0 KiB
C
81 lines
2.0 KiB
C
/*
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* ICPlus PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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*/
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#include <phy.h>
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/* IP101A/G - IP1001 */
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#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
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#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
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#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
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#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
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#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
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#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
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#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
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#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
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static int ip1001_config(struct phy_device *phydev)
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{
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int c;
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/* Enable Auto Power Saving mode */
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c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
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if (c < 0)
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return c;
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c |= IP1001_APS_ON;
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c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
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if (c < 0)
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return c;
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/* INTR pin used: speed/link/duplex will cause an interrupt */
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c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
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IP101A_G_IRQ_DEFAULT);
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if (c < 0)
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return c;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
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/*
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* Additional delay (2ns) used to adjust RX clock phase
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* at RGMII interface
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*/
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c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
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if (c < 0)
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return c;
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c |= IP1001_PHASE_SEL_MASK;
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c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
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c);
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if (c < 0)
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return c;
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}
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return 0;
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}
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static int ip1001_startup(struct phy_device *phydev)
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{
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genphy_update_link(phydev);
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genphy_parse_link(phydev);
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return 0;
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}
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static struct phy_driver IP1001_driver = {
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.name = "ICPlus IP1001",
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.uid = 0x02430d90,
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.mask = 0x0ffffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &ip1001_config,
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.startup = &ip1001_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_icplus_init(void)
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{
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phy_register(&IP1001_driver);
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return 0;
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}
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