656 lines
16 KiB
C
656 lines
16 KiB
C
/*
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* sh_eth.c - Driver for Renesas ethernet controler.
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*
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* Copyright (C) 2008, 2011 Renesas Solutions Corp.
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* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include "sh_eth.h"
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#ifndef CONFIG_SH_ETHER_USE_PORT
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# error "Please define CONFIG_SH_ETHER_USE_PORT"
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#endif
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#ifndef CONFIG_SH_ETHER_PHY_ADDR
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# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
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#endif
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#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
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#define flush_cache_wback(addr, len) \
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flush_dcache_range((u32)addr, (u32)(addr + len - 1))
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#else
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#define flush_cache_wback(...)
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#endif
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#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
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#define invalidate_cache(addr, len) \
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{ \
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u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
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u32 start, end; \
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\
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start = (u32)addr; \
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end = start + len; \
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start &= ~(line_size - 1); \
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end = ((end + line_size - 1) & ~(line_size - 1)); \
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\
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invalidate_dcache_range(start, end); \
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}
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#else
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#define invalidate_cache(...)
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#endif
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#define TIMEOUT_CNT 1000
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int sh_eth_send(struct eth_device *dev, void *packet, int len)
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{
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struct sh_eth_dev *eth = dev->priv;
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int port = eth->port, ret = 0, timeout;
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struct sh_eth_info *port_info = ð->port_info[port];
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if (!packet || len > 0xffff) {
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printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
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ret = -EINVAL;
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goto err;
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}
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/* packet must be a 4 byte boundary */
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if ((int)packet & 3) {
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printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
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ret = -EFAULT;
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goto err;
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}
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/* Update tx descriptor */
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flush_cache_wback(packet, len);
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port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
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port_info->tx_desc_cur->td1 = len << 16;
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/* Must preserve the end of descriptor list indication */
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if (port_info->tx_desc_cur->td0 & TD_TDLE)
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
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else
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
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/* Restart the transmitter if disabled */
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if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
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sh_eth_write(eth, EDTRR_TRNS, EDTRR);
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/* Wait until packet is transmitted */
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timeout = TIMEOUT_CNT;
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do {
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invalidate_cache(port_info->tx_desc_cur,
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sizeof(struct tx_desc_s));
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udelay(100);
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} while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
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if (timeout < 0) {
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printf(SHETHER_NAME ": transmit timeout\n");
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ret = -ETIMEDOUT;
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goto err;
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}
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port_info->tx_desc_cur++;
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if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
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port_info->tx_desc_cur = port_info->tx_desc_base;
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err:
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return ret;
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}
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int sh_eth_recv(struct eth_device *dev)
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{
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struct sh_eth_dev *eth = dev->priv;
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int port = eth->port, len = 0;
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struct sh_eth_info *port_info = ð->port_info[port];
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uchar *packet;
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/* Check if the rx descriptor is ready */
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invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
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if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
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/* Check for errors */
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if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
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len = port_info->rx_desc_cur->rd1 & 0xffff;
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packet = (uchar *)
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ADDR_TO_P2(port_info->rx_desc_cur->rd2);
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invalidate_cache(packet, len);
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NetReceive(packet, len);
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}
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/* Make current descriptor available again */
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if (port_info->rx_desc_cur->rd0 & RD_RDLE)
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port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
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else
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port_info->rx_desc_cur->rd0 = RD_RACT;
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/* Point to the next descriptor */
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port_info->rx_desc_cur++;
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if (port_info->rx_desc_cur >=
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port_info->rx_desc_base + NUM_RX_DESC)
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port_info->rx_desc_cur = port_info->rx_desc_base;
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}
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/* Restart the receiver if disabled */
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if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
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sh_eth_write(eth, EDRRR_R, EDRRR);
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return len;
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}
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static int sh_eth_reset(struct sh_eth_dev *eth)
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{
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#if defined(SH_ETH_TYPE_GETHER)
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int ret = 0, i;
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/* Start e-dmac transmitter and receiver */
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sh_eth_write(eth, EDSR_ENALL, EDSR);
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/* Perform a software reset and wait for it to complete */
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sh_eth_write(eth, EDMR_SRST, EDMR);
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for (i = 0; i < TIMEOUT_CNT ; i++) {
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if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
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break;
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udelay(1000);
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}
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if (i == TIMEOUT_CNT) {
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printf(SHETHER_NAME ": Software reset timeout\n");
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ret = -EIO;
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}
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return ret;
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#else
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sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
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udelay(3000);
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sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
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return 0;
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#endif
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}
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static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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{
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int port = eth->port, i, ret = 0;
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u32 tmp_addr;
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struct sh_eth_info *port_info = ð->port_info[port];
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struct tx_desc_s *cur_tx_desc;
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/*
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* Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
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*/
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port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
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sizeof(struct tx_desc_s) +
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TX_DESC_SIZE - 1);
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if (!port_info->tx_desc_malloc) {
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printf(SHETHER_NAME ": malloc failed\n");
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ret = -ENOMEM;
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goto err;
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}
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tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
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~(TX_DESC_SIZE - 1));
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flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
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port_info->tx_desc_cur = port_info->tx_desc_base;
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/* Initialize all descriptors */
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for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
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cur_tx_desc++, i++) {
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cur_tx_desc->td0 = 0x00;
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cur_tx_desc->td1 = 0x00;
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cur_tx_desc->td2 = 0x00;
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}
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/* Mark the end of the descriptors */
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cur_tx_desc--;
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cur_tx_desc->td0 |= TD_TDLE;
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/* Point the controller to the tx descriptor list. Must use physical
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addresses */
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sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
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sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
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sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
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#endif
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err:
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return ret;
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}
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static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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{
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int port = eth->port, i , ret = 0;
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struct sh_eth_info *port_info = ð->port_info[port];
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struct rx_desc_s *cur_rx_desc;
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u32 tmp_addr;
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u8 *rx_buf;
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/*
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* Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
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*/
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port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
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sizeof(struct rx_desc_s) +
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RX_DESC_SIZE - 1);
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if (!port_info->rx_desc_malloc) {
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printf(SHETHER_NAME ": malloc failed\n");
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ret = -ENOMEM;
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goto err;
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}
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tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
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~(RX_DESC_SIZE - 1));
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flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
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port_info->rx_desc_cur = port_info->rx_desc_base;
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/*
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* Allocate rx data buffers. They must be 32 bytes aligned and in
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* P2 area
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*/
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port_info->rx_buf_malloc = malloc(
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NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
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if (!port_info->rx_buf_malloc) {
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printf(SHETHER_NAME ": malloc failed\n");
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ret = -ENOMEM;
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goto err_buf_malloc;
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}
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tmp_addr = (u32)(((int)port_info->rx_buf_malloc
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+ (RX_BUF_ALIGNE_SIZE - 1)) &
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~(RX_BUF_ALIGNE_SIZE - 1));
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port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
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/* Initialize all descriptors */
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for (cur_rx_desc = port_info->rx_desc_base,
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rx_buf = port_info->rx_buf_base, i = 0;
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i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
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cur_rx_desc->rd0 = RD_RACT;
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cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
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cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
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}
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/* Mark the end of the descriptors */
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cur_rx_desc--;
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cur_rx_desc->rd0 |= RD_RDLE;
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/* Point the controller to the rx descriptor list */
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sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
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sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
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sh_eth_write(eth, RDFFR_RDLF, RDFFR);
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#endif
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return ret;
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err_buf_malloc:
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free(port_info->rx_desc_malloc);
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port_info->rx_desc_malloc = NULL;
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err:
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return ret;
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}
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static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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struct sh_eth_info *port_info = ð->port_info[port];
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if (port_info->tx_desc_malloc) {
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free(port_info->tx_desc_malloc);
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port_info->tx_desc_malloc = NULL;
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}
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}
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static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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struct sh_eth_info *port_info = ð->port_info[port];
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if (port_info->rx_desc_malloc) {
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free(port_info->rx_desc_malloc);
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port_info->rx_desc_malloc = NULL;
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}
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if (port_info->rx_buf_malloc) {
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free(port_info->rx_buf_malloc);
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port_info->rx_buf_malloc = NULL;
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}
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}
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static int sh_eth_desc_init(struct sh_eth_dev *eth)
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{
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int ret = 0;
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ret = sh_eth_tx_desc_init(eth);
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if (ret)
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goto err_tx_init;
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ret = sh_eth_rx_desc_init(eth);
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if (ret)
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goto err_rx_init;
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return ret;
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err_rx_init:
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sh_eth_tx_desc_free(eth);
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err_tx_init:
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return ret;
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}
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static int sh_eth_phy_config(struct sh_eth_dev *eth)
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{
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int port = eth->port, ret = 0;
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struct sh_eth_info *port_info = ð->port_info[port];
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struct eth_device *dev = port_info->dev;
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struct phy_device *phydev;
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phydev = phy_connect(
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miiphy_get_dev_by_name(dev->name),
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port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
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port_info->phydev = phydev;
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phy_config(phydev);
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return ret;
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}
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static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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{
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int port = eth->port, ret = 0;
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u32 val;
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struct sh_eth_info *port_info = ð->port_info[port];
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struct eth_device *dev = port_info->dev;
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struct phy_device *phy;
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/* Configure e-dmac registers */
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sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
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(EMDR_DESC | EDMR_EL), EDMR);
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sh_eth_write(eth, 0, EESIPR);
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sh_eth_write(eth, 0, TRSCER);
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sh_eth_write(eth, 0, TFTR);
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sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
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sh_eth_write(eth, RMCR_RST, RMCR);
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(eth, 0, RPADIR);
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#endif
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sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
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/* Configure e-mac registers */
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sh_eth_write(eth, 0, ECSIPR);
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/* Set Mac address */
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val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
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dev->enetaddr[2] << 8 | dev->enetaddr[3];
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sh_eth_write(eth, val, MAHR);
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val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
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sh_eth_write(eth, val, MALR);
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sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(eth, 0, PIPR);
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sh_eth_write(eth, APR_AP, APR);
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sh_eth_write(eth, MPR_MP, MPR);
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sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
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#endif
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#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
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sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
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sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
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#endif
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/* Configure phy */
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ret = sh_eth_phy_config(eth);
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if (ret) {
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printf(SHETHER_NAME ": phy config timeout\n");
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goto err_phy_cfg;
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}
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phy = port_info->phydev;
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ret = phy_startup(phy);
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if (ret) {
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printf(SHETHER_NAME ": phy startup failure\n");
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return ret;
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}
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val = 0;
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/* Set the transfer speed */
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if (phy->speed == 100) {
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printf(SHETHER_NAME ": 100Base/");
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(eth, GECMR_100B, GECMR);
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
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sh_eth_write(eth, 1, RTRATE);
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#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
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defined(CONFIG_R8A7791)
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val = ECMR_RTM;
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#endif
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} else if (phy->speed == 10) {
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printf(SHETHER_NAME ": 10Base/");
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(eth, GECMR_10B, GECMR);
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
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sh_eth_write(eth, 0, RTRATE);
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#endif
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}
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#if defined(SH_ETH_TYPE_GETHER)
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else if (phy->speed == 1000) {
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printf(SHETHER_NAME ": 1000Base/");
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sh_eth_write(eth, GECMR_1000B, GECMR);
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}
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#endif
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/* Check if full duplex mode is supported by the phy */
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if (phy->duplex) {
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printf("Full\n");
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sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
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ECMR);
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} else {
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printf("Half\n");
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sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
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}
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return ret;
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err_phy_cfg:
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return ret;
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}
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static void sh_eth_start(struct sh_eth_dev *eth)
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{
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/*
|
|
* Enable the e-dmac receiver only. The transmitter will be enabled when
|
|
* we have something to transmit
|
|
*/
|
|
sh_eth_write(eth, EDRRR_R, EDRRR);
|
|
}
|
|
|
|
static void sh_eth_stop(struct sh_eth_dev *eth)
|
|
{
|
|
sh_eth_write(eth, ~EDRRR_R, EDRRR);
|
|
}
|
|
|
|
int sh_eth_init(struct eth_device *dev, bd_t *bd)
|
|
{
|
|
int ret = 0;
|
|
struct sh_eth_dev *eth = dev->priv;
|
|
|
|
ret = sh_eth_reset(eth);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = sh_eth_desc_init(eth);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = sh_eth_config(eth, bd);
|
|
if (ret)
|
|
goto err_config;
|
|
|
|
sh_eth_start(eth);
|
|
|
|
return ret;
|
|
|
|
err_config:
|
|
sh_eth_tx_desc_free(eth);
|
|
sh_eth_rx_desc_free(eth);
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
void sh_eth_halt(struct eth_device *dev)
|
|
{
|
|
struct sh_eth_dev *eth = dev->priv;
|
|
sh_eth_stop(eth);
|
|
}
|
|
|
|
int sh_eth_initialize(bd_t *bd)
|
|
{
|
|
int ret = 0;
|
|
struct sh_eth_dev *eth = NULL;
|
|
struct eth_device *dev = NULL;
|
|
|
|
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
|
|
if (!eth) {
|
|
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
|
|
if (!dev) {
|
|
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
memset(dev, 0, sizeof(struct eth_device));
|
|
memset(eth, 0, sizeof(struct sh_eth_dev));
|
|
|
|
eth->port = CONFIG_SH_ETHER_USE_PORT;
|
|
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
|
|
|
|
dev->priv = (void *)eth;
|
|
dev->iobase = 0;
|
|
dev->init = sh_eth_init;
|
|
dev->halt = sh_eth_halt;
|
|
dev->send = sh_eth_send;
|
|
dev->recv = sh_eth_recv;
|
|
eth->port_info[eth->port].dev = dev;
|
|
|
|
sprintf(dev->name, SHETHER_NAME);
|
|
|
|
/* Register Device to EtherNet subsystem */
|
|
eth_register(dev);
|
|
|
|
bb_miiphy_buses[0].priv = eth;
|
|
miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
|
|
|
|
if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
|
|
puts("Please set MAC address\n");
|
|
|
|
return ret;
|
|
|
|
err:
|
|
if (dev)
|
|
free(dev);
|
|
|
|
if (eth)
|
|
free(eth);
|
|
|
|
printf(SHETHER_NAME ": Failed\n");
|
|
return ret;
|
|
}
|
|
|
|
/******* for bb_miiphy *******/
|
|
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
|
|
sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
|
|
sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
|
|
if (v)
|
|
sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
|
|
else
|
|
sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
|
|
*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
|
|
if (v)
|
|
sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
|
|
else
|
|
sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
|
|
{
|
|
udelay(10);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct bb_miiphy_bus bb_miiphy_buses[] = {
|
|
{
|
|
.name = "sh_eth",
|
|
.init = sh_eth_bb_init,
|
|
.mdio_active = sh_eth_bb_mdio_active,
|
|
.mdio_tristate = sh_eth_bb_mdio_tristate,
|
|
.set_mdio = sh_eth_bb_set_mdio,
|
|
.get_mdio = sh_eth_bb_get_mdio,
|
|
.set_mdc = sh_eth_bb_set_mdc,
|
|
.delay = sh_eth_bb_delay,
|
|
}
|
|
};
|
|
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
|