55 lines
1.1 KiB
C
55 lines
1.1 KiB
C
/*
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* (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
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*
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* Developed for DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_DSP
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#include <asm/io.h>
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/* This test verifies DSP status bits in FPGA */
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DECLARE_GLOBAL_DATA_PTR;
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#define DSP_STATUS_REG 0xC4000008
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#define FPGA_STATUS_REG 0xC400000C
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int dsp_post_test(int flags)
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{
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uint old_value;
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uint read_value;
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int ret;
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/* momorize fpga status */
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old_value = in_be32((void *)FPGA_STATUS_REG);
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/* enable outputs */
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out_be32((void *)FPGA_STATUS_REG, 0x30);
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/* generate sync signal */
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out_be32((void *)DSP_STATUS_REG, 0x300);
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udelay(5);
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out_be32((void *)DSP_STATUS_REG, 0);
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udelay(500);
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/* read status */
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ret = 0;
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read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
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if (read_value != 0x03) {
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post_log("\nDSP status read %08X\n", read_value);
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ret = 1;
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}
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/* restore fpga status */
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out_be32((void *)FPGA_STATUS_REG, old_value);
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */
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