226 lines
6.4 KiB
C
226 lines
6.4 KiB
C
/*
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* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <serial.h>
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#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
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#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
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#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
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#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
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#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
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#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
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#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
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/* Some clock/baud constants */
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#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */
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#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */
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struct uart_zynq {
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u32 control; /* Control Register [8:0] */
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u32 mode; /* Mode Register [10:0] */
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u32 reserved1[4];
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u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
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u32 reserved2[4];
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u32 channel_sts; /* Channel Status [11:0] */
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u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
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u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
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};
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static struct uart_zynq *uart_zynq_ports[2] = {
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#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
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[0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
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#endif
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#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
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[1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
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#endif
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};
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struct uart_zynq_params {
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u32 baudrate;
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u32 clock;
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};
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static struct uart_zynq_params uart_zynq_ports_param[2] = {
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#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
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[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
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[0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
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#endif
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#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
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[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
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[1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
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#endif
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};
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/* Set up the baud rate in gd struct */
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static void uart_zynq_serial_setbrg(const int port)
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{
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/* Calculation results. */
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unsigned int calc_bauderror, bdiv, bgen;
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unsigned long calc_baud = 0;
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unsigned long baud = uart_zynq_ports_param[port].baudrate;
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unsigned long clock = uart_zynq_ports_param[port].clock;
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struct uart_zynq *regs = uart_zynq_ports[port];
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/* master clock
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* Baud rate = ------------------
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* bgen * (bdiv + 1)
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*
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* Find acceptable values for baud generation.
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*/
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for (bdiv = 4; bdiv < 255; bdiv++) {
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bgen = clock / (baud * (bdiv + 1));
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if (bgen < 2 || bgen > 65535)
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continue;
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calc_baud = clock / (bgen * (bdiv + 1));
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/*
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* Use first calculated baudrate with
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* an acceptable (<3%) error
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*/
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if (baud > calc_baud)
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calc_bauderror = baud - calc_baud;
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else
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calc_bauderror = calc_baud - baud;
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if (((calc_bauderror * 100) / baud) < 3)
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break;
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}
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writel(bdiv, ®s->baud_rate_divider);
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writel(bgen, ®s->baud_rate_gen);
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}
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/* Initialize the UART, with...some settings. */
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static int uart_zynq_serial_init(const int port)
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{
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struct uart_zynq *regs = uart_zynq_ports[port];
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if (!regs)
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return -1;
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/* RX/TX enabled & reset */
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writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
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ZYNQ_UART_CR_RXRST, ®s->control);
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writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
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uart_zynq_serial_setbrg(port);
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return 0;
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}
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static void uart_zynq_serial_putc(const char c, const int port)
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{
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struct uart_zynq *regs = uart_zynq_ports[port];
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while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
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WATCHDOG_RESET();
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if (c == '\n') {
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writel('\r', ®s->tx_rx_fifo);
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while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
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WATCHDOG_RESET();
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}
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writel(c, ®s->tx_rx_fifo);
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}
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static void uart_zynq_serial_puts(const char *s, const int port)
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{
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while (*s)
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uart_zynq_serial_putc(*s++, port);
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}
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static int uart_zynq_serial_tstc(const int port)
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{
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struct uart_zynq *regs = uart_zynq_ports[port];
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return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
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}
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static int uart_zynq_serial_getc(const int port)
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{
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struct uart_zynq *regs = uart_zynq_ports[port];
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while (!uart_zynq_serial_tstc(port))
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WATCHDOG_RESET();
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return readl(®s->tx_rx_fifo);
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}
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/* Multi serial device functions */
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#define DECLARE_PSSERIAL_FUNCTIONS(port) \
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int uart_zynq##port##_init(void) \
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{ return uart_zynq_serial_init(port); } \
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void uart_zynq##port##_setbrg(void) \
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{ return uart_zynq_serial_setbrg(port); } \
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int uart_zynq##port##_getc(void) \
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{ return uart_zynq_serial_getc(port); } \
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int uart_zynq##port##_tstc(void) \
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{ return uart_zynq_serial_tstc(port); } \
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void uart_zynq##port##_putc(const char c) \
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{ uart_zynq_serial_putc(c, port); } \
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void uart_zynq##port##_puts(const char *s) \
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{ uart_zynq_serial_puts(s, port); }
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/* Serial device descriptor */
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#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
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.name = __name, \
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.start = uart_zynq##port##_init, \
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.stop = NULL, \
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.setbrg = uart_zynq##port##_setbrg, \
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.getc = uart_zynq##port##_getc, \
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.tstc = uart_zynq##port##_tstc, \
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.putc = uart_zynq##port##_putc, \
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.puts = uart_zynq##port##_puts, \
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}
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DECLARE_PSSERIAL_FUNCTIONS(0);
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struct serial_device uart_zynq_serial0_device =
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INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
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DECLARE_PSSERIAL_FUNCTIONS(1);
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struct serial_device uart_zynq_serial1_device =
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INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
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__weak struct serial_device *default_serial_console(void)
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{
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if (uart_zynq_ports[0])
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return &uart_zynq_serial0_device;
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if (uart_zynq_ports[1])
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return &uart_zynq_serial1_device;
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return NULL;
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}
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void zynq_serial_initalize(void)
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{
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#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
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serial_register(&uart_zynq_serial0_device);
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#endif
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#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
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serial_register(&uart_zynq_serial1_device);
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#endif
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}
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