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Marek Vasut bfa89d2ba8 arm: socfpga: Fix FPGA bitstream programming routine 
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
 		2015-08-08 14:14:04 +02:00
..
ACEX1K.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
Makefile arm: socfpga: fpga: Add SoCFPGA FPGA programming interface 2014-10-06 17:46:50 +02:00
altera.c arm: socfpga: fpga: Add SoCFPGA FPGA programming interface 2014-10-06 17:46:50 +02:00
cyclon2.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
fpga.c fpga: Export fpga_get_desc for SPL 2015-01-21 10:25:02 +01:00
ivm_core.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
lattice.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
socfpga.c arm: socfpga: Fix FPGA bitstream programming routine 2015-08-08 14:14:04 +02:00
spartan2.c fpga: Define bitstream type based on command selection 2014-05-20 15:23:46 +02:00
spartan3.c fpga: Define bitstream type based on command selection 2014-05-20 15:23:46 +02:00
stratixII.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
virtex2.c fpga: Define bitstream type based on command selection 2014-05-20 15:23:46 +02:00
xilinx.c fpga: xilinx: Show fpga info if defined 2015-01-21 10:25:43 +01:00
zynqpl.c fs: API changes enabling extra parameter to return size of type loff_t 2014-11-23 06:49:04 -05:00