145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Samsung Electronics
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* Przemyslaw Marczak <p.marczak@samsung.com>
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <adc.h>
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#include <asm/arch/adc.h>
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struct exynos_adc_priv {
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int active_channel;
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struct exynos_adc_v2 *regs;
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};
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int exynos_adc_channel_data(struct udevice *dev, int channel,
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unsigned int *data)
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{
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struct exynos_adc_priv *priv = dev_get_priv(dev);
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struct exynos_adc_v2 *regs = priv->regs;
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if (channel != priv->active_channel) {
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pr_err("Requested channel is not active!");
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return -EINVAL;
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}
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if (ADC_V2_GET_STATUS_FLAG(readl(®s->status)) != FLAG_CONV_END)
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return -EBUSY;
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*data = readl(®s->dat) & ADC_V2_DAT_MASK;
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return 0;
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}
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int exynos_adc_start_channel(struct udevice *dev, int channel)
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{
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struct exynos_adc_priv *priv = dev_get_priv(dev);
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struct exynos_adc_v2 *regs = priv->regs;
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unsigned int cfg;
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/* Choose channel */
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cfg = readl(®s->con2);
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cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK;
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cfg |= ADC_V2_CON2_CHAN_SEL(channel);
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writel(cfg, ®s->con2);
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/* Start conversion */
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cfg = readl(®s->con1);
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writel(cfg | ADC_V2_CON1_STC_EN, ®s->con1);
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priv->active_channel = channel;
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return 0;
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}
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int exynos_adc_stop(struct udevice *dev)
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{
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struct exynos_adc_priv *priv = dev_get_priv(dev);
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struct exynos_adc_v2 *regs = priv->regs;
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unsigned int cfg;
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/* Stop conversion */
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cfg = readl(®s->con1);
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cfg &= ~ADC_V2_CON1_STC_EN;
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writel(cfg, ®s->con1);
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priv->active_channel = -1;
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return 0;
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}
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int exynos_adc_probe(struct udevice *dev)
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{
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struct exynos_adc_priv *priv = dev_get_priv(dev);
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struct exynos_adc_v2 *regs = priv->regs;
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unsigned int cfg;
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/* Check HW version */
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if (readl(®s->version) != ADC_V2_VERSION) {
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pr_err("This driver supports only ADC v2!");
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return -ENXIO;
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}
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/* ADC Reset */
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writel(ADC_V2_CON1_SOFT_RESET, ®s->con1);
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/* Disable INT - will read status only */
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writel(0x0, ®s->int_en);
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/* CON2 - set conversion parameters */
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cfg = ADC_V2_CON2_C_TIME(3); /* Conversion times: (1 << 3) = 8 */
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cfg |= ADC_V2_CON2_OSEL(OSEL_BINARY);
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cfg |= ADC_V2_CON2_ESEL(ESEL_ADC_EVAL_TIME_20CLK);
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cfg |= ADC_V2_CON2_HIGHF(HIGHF_CONV_RATE_600KSPS);
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writel(cfg, ®s->con2);
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priv->active_channel = -1;
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return 0;
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}
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int exynos_adc_of_to_plat(struct udevice *dev)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct exynos_adc_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr_ptr(dev);
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if (priv->regs == (struct exynos_adc_v2 *)FDT_ADDR_T_NONE) {
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pr_err("Dev: %s - can't get address!", dev->name);
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return -ENODATA;
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}
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uc_pdata->data_mask = ADC_V2_DAT_MASK;
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uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
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uc_pdata->data_timeout_us = ADC_V2_CONV_TIMEOUT_US;
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/* Mask available channel bits: [0:9] */
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uc_pdata->channel_mask = (2 << ADC_V2_MAX_CHANNEL) - 1;
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return 0;
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}
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static const struct adc_ops exynos_adc_ops = {
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.start_channel = exynos_adc_start_channel,
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.channel_data = exynos_adc_channel_data,
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.stop = exynos_adc_stop,
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};
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static const struct udevice_id exynos_adc_ids[] = {
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{ .compatible = "samsung,exynos-adc-v2" },
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{ }
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};
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U_BOOT_DRIVER(exynos_adc) = {
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.name = "exynos-adc",
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.id = UCLASS_ADC,
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.of_match = exynos_adc_ids,
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.ops = &exynos_adc_ops,
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.probe = exynos_adc_probe,
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.of_to_plat = exynos_adc_of_to_plat,
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.priv_auto = sizeof(struct exynos_adc_priv),
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};
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