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Sinthu Raja 7413e67575 dt-bindings: ti-serdes-mux: Add USB Type C swap defines for J721S2 SoC 
Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C
lane swap if Lanes 1 and 3 are connected to the SerDes IP's USB PHY.
Remove the defines that state the Lane 0 and Lane 2 IPs are unused,
and instead define the Type C swap configuration macro.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
 		2023-06-23 14:59:07 +05:30
..
mux.h
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ti-serdes.h dt-bindings: ti-serdes-mux: Add USB Type C swap defines for J721S2 SoC 2023-06-23 14:59:07 +05:30