23 lines
577 B
C
23 lines
577 B
C
/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_RISCV_CACHE_H
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#define _ASM_RISCV_CACHE_H
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/*
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* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
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* We use that value for aligning DMA buffers unless the board config has
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* specified an alternate cache line size.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 32
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#endif
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#endif /* _ASM_RISCV_CACHE_H */
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