101 lines
4.4 KiB
Plaintext
101 lines
4.4 KiB
Plaintext
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Table of interleaving modes supported in cpu/8xxx/ddr/
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======================================================
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+-------------+---------------------------------------------------------+
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| | Rank Interleaving |
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| +--------+-----------+-----------+------------+-----------+
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|Memory | | | | 2x2 | 4x1 |
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|Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
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|Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
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+-------------+--------+-----------+-----------+------------+-----------+
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|None | Yes | Yes | Yes | Yes | Yes |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Cacheline | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Page | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Bank | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Superbank | No | Yes | No | No, Only(*)| Yes |
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| | | | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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(*) Although the hardware can be configured with memory controller
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interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
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from each controller. {CS2+CS3} on each controller are only rank
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interleaved on that controller.
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For memory controller interleaving, identical DIMMs are suggested. Software
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doesn't check the size or organization of interleaved DIMMs.
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The ways to configure the ddr interleaving mode
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==============================================
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1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
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under "CONFIG_EXTRA_ENV_SETTINGS", like:
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=bank" \
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......
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2. Run u-boot "setenv" command to configure the memory interleaving mode.
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Either numerical or string value is accepted.
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# disable memory controller interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=null"
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# cacheline interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
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# page interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=page"
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# bank interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
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# superbank
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setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
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# disable bank (chip-select) interleaving
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setenv hwconfig "fsl_ddr:bank_intlv=null"
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# bank(chip-select) interleaving cs0+cs1
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setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
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# bank(chip-select) interleaving cs2+cs3
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setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
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# bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
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setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
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# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
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setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
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Memory controller address hashing
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==================================
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If the DDR controller supports address hashing, it can be enabled by hwconfig.
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Syntax is:
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hwconfig=fsl_ddr:addr_hash=true
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Memory testing options for mpc85xx
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==================================
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1. Memory test can be done once U-boot prompt comes up using mtest, or
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2. Memory test can be done with Power-On-Self-Test function, activated at
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compile time.
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In order to enable the POST memory test, CONFIG_POST needs to be
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defined in board configuraiton header file. By default, POST memory test
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performs a fast test. A slow test can be enabled by changing the flag at
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compiling time. To test memory bigger than 2GB, 36BIT support is needed.
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Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
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window to physical address so that all physical memory can be tested.
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Combination of hwconfig
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=======================
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Hwconfig can be combined with multiple parameters, for example, on a supported
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platform
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hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3
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