ef87cab664
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com> |
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| .. | ||
| Makefile | ||
| arm_ddr_gen3.c | ||
| ctrl_regs.c | ||
| ddr1_dimm_params.c | ||
| ddr2_dimm_params.c | ||
| ddr3_dimm_params.c | ||
| ddr4_dimm_params.c | ||
| fsl_ddr_gen4.c | ||
| interactive.c | ||
| lc_common_dimm_params.c | ||
| main.c | ||
| mpc85xx_ddr_gen1.c | ||
| mpc85xx_ddr_gen2.c | ||
| mpc85xx_ddr_gen3.c | ||
| mpc86xx_ddr.c | ||
| options.c | ||
| util.c | ||