586 lines
14 KiB
C
586 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
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*/
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#define LOG_CATEGORY UCLASS_CLK
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#include <common.h>
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#include <dm.h>
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/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
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#include <div64.h>
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#include <log.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/k210-sysctl.h>
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#include <kendryte/pll.h>
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#define CLK_K210_PLL "k210_clk_pll"
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#ifdef CONFIG_CLK_K210_SET_RATE
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static int k210_pll_enable(struct clk *clk);
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static int k210_pll_disable(struct clk *clk);
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/*
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* The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
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* General-Purpose PLL. The logical layout of the PLL with internal feedback is
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* approximately the following:
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*
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* +---------------+
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* |reference clock|
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* +---------------+
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* |
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* v
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* +--+
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* |/r|
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* +--+
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* |
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* v
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* +-------------+
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* |divided clock|
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* +-------------+
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* |
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* v
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* +--------------+
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* |phase detector|<---+
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* +--------------+ |
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* | |
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* v +--------------+
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* +---+ |feedback clock|
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* |VCO| +--------------+
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* +---+ ^
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* | +--+ |
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* +--->|/f|---+
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* | +--+
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* v
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* +---+
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* |/od|
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* +---+
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* |
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* v
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* +------+
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* |output|
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* +------+
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*
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* The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
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* the effect of the division by f is to multiply the input frequency. The
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* equation for the output rate is
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* rate = (rate_in * f) / (r * od).
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* Moving knowns to one side of the equation, we get
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* rate / rate_in = f / (r * od)
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* Rearranging slightly,
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* abs_error = abs((rate / rate_in) - (f / (r * od))).
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* To get relative, error, we divide by the expected ratio
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* error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
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* Simplifying,
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* error = abs(1 - f / (r * od)) / (rate / rate_in)
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* error = abs(1 - (f * rate_in) / (r * od * rate))
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* Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
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* error = abs((f * inv_ratio) / (r * od) - 1)
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* This is the error used in evaluating parameters.
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*
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* r and od are four bits each, while f is six bits. Because r and od are
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* multiplied together, instead of the full 256 values possible if both bits
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* were used fully, there are only 97 distinct products. Combined with f, there
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* are 6208 theoretical settings for the PLL. However, most of these settings
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* can be ruled out immediately because they do not have the correct ratio.
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*
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* In addition to the constraint of approximating the desired ratio, parameters
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* must also keep internal pll frequencies within acceptable ranges. The divided
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* clock's minimum and maximum frequencies have a ratio of around 128. This
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* leaves fairly substantial room to work with, especially since the only
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* affected parameter is r. The VCO's minimum and maximum frequency have a ratio
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* of 5, which is considerably more restrictive.
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*
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* The r and od factors are stored in a table. This is to make it easy to find
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* the next-largest product. Some products have multiple factorizations, but
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* only when one factor has at least a 2.5x ratio to the factors of the other
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* factorization. This is because any smaller ratio would not make a difference
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* when ensuring the VCO's frequency is within spec.
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*
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* Throughout the calculation function, fixed point arithmetic is used. Because
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* the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
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* 32.32 fixed-point numbers are used to represent ratios. In general, to
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* implement division, the numerator is first multiplied by 2^32. This gives a
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* result where the whole number part is in the upper 32 bits, and the fraction
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* is in the lower 32 bits.
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*
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* In general, rounding is done to the closest integer. This helps find the best
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* approximation for the ratio. Rounding in one direction (e.g down) could cause
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* the function to miss a better ratio with one of the parameters increased by
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* one.
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*/
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/*
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* The factors table was generated with the following python code:
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*
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* def p(x, y):
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* return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
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*
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* factors = {}
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* for i in range(1, 17):
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* for j in range(1, 17):
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* fs = factors.get(i*j) or []
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* if fs == [] or all([
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* (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
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* for (x, y) in fs]):
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* fs.append((i, j))
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* factors[i*j] = fs
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*
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* for k, l in sorted(factors.items()):
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* for v in l:
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* print("PACK(%s, %s)," % v)
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*/
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#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
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#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
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#define UNPACK_OD(val) (((val) & 0xF) + 1)
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static const u8 factors[] = {
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PACK(1, 1),
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PACK(1, 2),
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PACK(1, 3),
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PACK(1, 4),
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PACK(1, 5),
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PACK(1, 6),
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PACK(1, 7),
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PACK(1, 8),
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PACK(1, 9),
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PACK(3, 3),
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PACK(1, 10),
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PACK(1, 11),
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PACK(1, 12),
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PACK(3, 4),
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PACK(1, 13),
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PACK(1, 14),
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PACK(1, 15),
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PACK(3, 5),
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PACK(1, 16),
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PACK(4, 4),
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PACK(2, 9),
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PACK(2, 10),
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PACK(3, 7),
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PACK(2, 11),
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PACK(2, 12),
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PACK(5, 5),
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PACK(2, 13),
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PACK(3, 9),
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PACK(2, 14),
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PACK(2, 15),
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PACK(2, 16),
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PACK(3, 11),
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PACK(5, 7),
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PACK(3, 12),
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PACK(3, 13),
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PACK(4, 10),
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PACK(3, 14),
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PACK(4, 11),
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PACK(3, 15),
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PACK(3, 16),
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PACK(7, 7),
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PACK(5, 10),
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PACK(4, 13),
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PACK(6, 9),
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PACK(5, 11),
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PACK(4, 14),
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PACK(4, 15),
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PACK(7, 9),
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PACK(4, 16),
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PACK(5, 13),
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PACK(6, 11),
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PACK(5, 14),
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PACK(6, 12),
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PACK(5, 15),
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PACK(7, 11),
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PACK(6, 13),
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PACK(5, 16),
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PACK(9, 9),
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PACK(6, 14),
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PACK(8, 11),
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PACK(6, 15),
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PACK(7, 13),
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PACK(6, 16),
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PACK(7, 14),
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PACK(9, 11),
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PACK(10, 10),
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PACK(8, 13),
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PACK(7, 15),
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PACK(9, 12),
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PACK(10, 11),
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PACK(7, 16),
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PACK(9, 13),
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PACK(8, 15),
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PACK(11, 11),
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PACK(9, 14),
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PACK(8, 16),
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PACK(10, 13),
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PACK(11, 12),
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PACK(9, 15),
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PACK(10, 14),
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PACK(11, 13),
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PACK(9, 16),
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PACK(10, 15),
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PACK(11, 14),
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PACK(12, 13),
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PACK(10, 16),
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PACK(11, 15),
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PACK(12, 14),
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PACK(13, 13),
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PACK(11, 16),
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PACK(12, 15),
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PACK(13, 14),
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PACK(12, 16),
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PACK(13, 15),
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PACK(14, 14),
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PACK(13, 16),
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PACK(14, 15),
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PACK(14, 16),
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PACK(15, 15),
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PACK(15, 16),
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PACK(16, 16),
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};
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TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
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struct k210_pll_config *best)
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{
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int i;
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s64 error, best_error;
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u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
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u64 max_r;
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u64 r, f, od;
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/*
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* Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
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* VCO frequency. These are not the same limits as below because od can
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* reduce the output frequency by 16.
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*/
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if (rate > 1750000000 || rate < 21250000)
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return -EINVAL;
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/* Similar restrictions on the input rate */
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if (rate_in > 1750000000 || rate_in < 13300000)
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return -EINVAL;
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ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
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inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
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/* Can't increase by more than 64 or reduce by more than 256 */
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if (rate > rate_in && ratio > (64ULL << 32))
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return -EINVAL;
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else if (rate <= rate_in && inv_ratio > (256ULL << 32))
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return -EINVAL;
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/*
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* The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
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* MHz. There is no minimum, since the only way to get a higher input
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* clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
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* cannot output frequencies greater than 1.75 GHz, the minimum would
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* never be greater than one.
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*/
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max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
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/* Variables get immediately incremented, so start at -1th iteration */
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i = -1;
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f = 0;
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r = 0;
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od = 0;
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best_error = S64_MAX;
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error = best_error;
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/* do-while here so we always try at least one ratio */
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do {
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/*
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* Whether we swapped r and od while enforcing frequency limits
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*/
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bool swapped = false;
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u64 last_od = od;
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u64 last_r = r;
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/*
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* Try the next largest value for f (or r and od) and
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* recalculate the other parameters based on that
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*/
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if (rate > rate_in) {
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/*
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* Skip factors of the same product if we already tried
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* out that product
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*/
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do {
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i++;
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r = UNPACK_R(factors[i]);
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od = UNPACK_OD(factors[i]);
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} while (i + 1 < ARRAY_SIZE(factors) &&
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r * od == last_r * last_od);
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/* Round close */
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f = (r * od * ratio + BIT(31)) >> 32;
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if (f > 64)
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f = 64;
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} else {
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u64 tmp = ++f * inv_ratio;
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bool round_up = !!(tmp & BIT(31));
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u32 goal = (tmp >> 32) + round_up;
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u32 err, last_err;
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/* Get the next r/od pair in factors */
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while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
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i++;
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r = UNPACK_R(factors[i]);
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od = UNPACK_OD(factors[i]);
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}
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/*
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* This is a case of double rounding. If we rounded up
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* above, we need to round down (in cases of ties) here.
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* This prevents off-by-one errors resulting from
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* choosing X+2 over X when X.Y rounds up to X+1 and
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* there is no r * od = X+1. For the converse, when X.Y
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* is rounded down to X, we should choose X+1 over X-1.
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*/
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err = abs(r * od - goal);
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last_err = abs(last_r * last_od - goal);
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if (last_err < err || (round_up && last_err == err)) {
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i--;
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r = last_r;
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od = last_od;
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}
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}
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/*
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* Enforce limits on internal clock frequencies. If we
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* aren't in spec, try swapping r and od. If everything is
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* in-spec, calculate the relative error.
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*/
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while (true) {
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/*
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* Whether the intermediate frequencies are out-of-spec
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*/
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bool out_of_spec = false;
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if (r > max_r) {
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out_of_spec = true;
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} else {
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/*
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* There is no way to only divide once; we need
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* to examine the frequency with and without the
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* effect of od.
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*/
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u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
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if (vco > 1750000000 || vco < 340000000)
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out_of_spec = true;
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}
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if (out_of_spec) {
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if (!swapped) {
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u64 tmp = r;
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r = od;
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od = tmp;
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swapped = true;
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continue;
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} else {
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/*
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* Try looking ahead to see if there are
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* additional factors for the same
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* product.
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*/
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if (i + 1 < ARRAY_SIZE(factors)) {
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u64 new_r, new_od;
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i++;
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new_r = UNPACK_R(factors[i]);
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new_od = UNPACK_OD(factors[i]);
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if (r * od == new_r * new_od) {
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r = new_r;
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od = new_od;
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swapped = false;
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continue;
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}
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i--;
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}
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break;
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}
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}
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error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
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/* The lower 16 bits are spurious */
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error = abs((error - BIT(32))) >> 16;
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if (error < best_error) {
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best->r = r;
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best->f = f;
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best->od = od;
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best_error = error;
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}
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break;
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}
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} while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
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if (best_error == S64_MAX)
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return -EINVAL;
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log_debug("best error %lld\n", best_error);
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return 0;
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}
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static ulong k210_pll_set_rate(struct clk *clk, ulong rate)
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{
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int err;
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long long rate_in = clk_get_parent_rate(clk);
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struct k210_pll_config config = {};
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struct k210_pll *pll = to_k210_pll(clk);
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u32 reg;
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if (rate_in < 0)
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return rate_in;
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log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n",
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rate, rate_in);
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err = k210_pll_calc_config(rate, rate_in, &config);
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if (err)
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return err;
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log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
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/*
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* Don't use clk_disable as it might not actually disable the pll due to
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* refcounting
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*/
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k210_pll_disable(clk);
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reg = readl(pll->reg);
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reg &= ~K210_PLL_CLKR
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& ~K210_PLL_CLKF
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& ~K210_PLL_CLKOD
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& ~K210_PLL_BWADJ;
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reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
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| FIELD_PREP(K210_PLL_CLKF, config.f - 1)
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| FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
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| FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
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writel(reg, pll->reg);
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err = k210_pll_enable(clk);
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if (err)
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return err;
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serial_setbrg();
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return clk_get_rate(clk);
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}
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#endif /* CONFIG_CLK_K210_SET_RATE */
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static ulong k210_pll_get_rate(struct clk *clk)
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{
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long long rate_in = clk_get_parent_rate(clk);
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struct k210_pll *pll = to_k210_pll(clk);
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u64 r, f, od;
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u32 reg = readl(pll->reg);
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if (rate_in < 0 || (reg & K210_PLL_BYPASS))
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return rate_in;
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if (!(reg & K210_PLL_PWRD))
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return 0;
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r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
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f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
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od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
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return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
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}
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/*
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* Wait for the PLL to be locked. If the PLL is not locked, try clearing the
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* slip before retrying
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*/
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static void k210_pll_waitfor_lock(struct k210_pll *pll)
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{
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u32 mask = GENMASK(pll->width - 1, 0) << pll->shift;
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while (true) {
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u32 reg = readl(pll->lock);
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if ((reg & mask) == mask)
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break;
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reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
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writel(reg, pll->lock);
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}
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}
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/* Adapted from sysctl_pll_enable */
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static int k210_pll_enable(struct clk *clk)
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{
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struct k210_pll *pll = to_k210_pll(clk);
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u32 reg = readl(pll->reg);
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if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
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!(reg & K210_PLL_RESET))
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return 0;
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|
|
reg |= K210_PLL_PWRD;
|
|
writel(reg, pll->reg);
|
|
|
|
/* Ensure reset is low before asserting it */
|
|
reg &= ~K210_PLL_RESET;
|
|
writel(reg, pll->reg);
|
|
reg |= K210_PLL_RESET;
|
|
writel(reg, pll->reg);
|
|
nop();
|
|
nop();
|
|
reg &= ~K210_PLL_RESET;
|
|
writel(reg, pll->reg);
|
|
|
|
k210_pll_waitfor_lock(pll);
|
|
|
|
reg &= ~K210_PLL_BYPASS;
|
|
reg |= K210_PLL_EN;
|
|
writel(reg, pll->reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int k210_pll_disable(struct clk *clk)
|
|
{
|
|
struct k210_pll *pll = to_k210_pll(clk);
|
|
u32 reg = readl(pll->reg);
|
|
|
|
/*
|
|
* Bypassing before powering off is important so child clocks don't stop
|
|
* working. This is especially important for pll0, the indirect parent
|
|
* of the cpu clock.
|
|
*/
|
|
reg |= K210_PLL_BYPASS;
|
|
writel(reg, pll->reg);
|
|
|
|
reg &= ~K210_PLL_PWRD;
|
|
reg &= ~K210_PLL_EN;
|
|
writel(reg, pll->reg);
|
|
return 0;
|
|
}
|
|
|
|
const struct clk_ops k210_pll_ops = {
|
|
.get_rate = k210_pll_get_rate,
|
|
#ifdef CONFIG_CLK_K210_SET_RATE
|
|
.set_rate = k210_pll_set_rate,
|
|
#endif
|
|
.enable = k210_pll_enable,
|
|
.disable = k210_pll_disable,
|
|
};
|
|
|
|
struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
|
|
struct k210_pll *pll)
|
|
{
|
|
int ret;
|
|
struct clk *clk = &pll->clk;
|
|
|
|
ret = clk_register(clk, CLK_K210_PLL, name, parent_name);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
return clk;
|
|
}
|
|
|
|
U_BOOT_DRIVER(k210_pll) = {
|
|
.name = CLK_K210_PLL,
|
|
.id = UCLASS_CLK,
|
|
.ops = &k210_pll_ops,
|
|
};
|