275 lines
6.7 KiB
C
275 lines
6.7 KiB
C
/*
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* Copyright (c) 2012 The Chromium OS Authors.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
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* through the PCI bus. Each PCI device has 256 bytes of configuration space,
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* consisting of a standard header and a device-specific set of registers. PCI
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* bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
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* other things). Within the PCI configuration space, the GPIOBASE register
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* tells us where in the device's I/O region we can find more registers to
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* actually access the GPIOs.
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*
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* PCI bus/device/function 0:1f:0 => PCI config registers
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* PCI config register "GPIOBASE"
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* PCI I/O space + [GPIOBASE] => start of GPIO registers
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* GPIO registers => gpio pin function, direction, value
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*
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*
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* Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
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* ICH versions have more, but the decoding the matrix that describes them is
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* absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
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* but they will ONLY work for certain unspecified chipsets because the offset
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* from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
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* reserved or subject to arcane restrictions.
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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/* Where in config space is the register that points to the GPIO registers? */
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#define PCI_CFG_GPIOBASE 0x48
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#define NUM_BANKS 3
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/* Within the I/O space, where are the registers to control the GPIOs? */
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static struct {
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u8 use_sel;
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u8 io_sel;
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u8 lvl;
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} gpio_bank[NUM_BANKS] = {
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{ 0x00, 0x04, 0x0c }, /* Bank 0 */
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{ 0x30, 0x34, 0x38 }, /* Bank 1 */
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{ 0x40, 0x44, 0x48 } /* Bank 2 */
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};
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static pci_dev_t dev; /* handle for 0:1f:0 */
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static u32 gpiobase; /* offset into I/O space */
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static int found_it_once; /* valid GPIO device? */
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static u32 lock[NUM_BANKS]; /* "lock" for access to pins */
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static int bad_arg(int num, int *bank, int *bitnum)
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{
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int i = num / 32;
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int j = num % 32;
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if (num < 0 || i > NUM_BANKS) {
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debug("%s: bogus gpio num: %d\n", __func__, num);
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return -1;
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}
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*bank = i;
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*bitnum = j;
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return 0;
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}
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static int mark_gpio(int bank, int bitnum)
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{
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if (lock[bank] & (1UL << bitnum)) {
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debug("%s: %d.%d already marked\n", __func__, bank, bitnum);
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return -1;
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}
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lock[bank] |= (1 << bitnum);
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return 0;
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}
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static void clear_gpio(int bank, int bitnum)
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{
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lock[bank] &= ~(1 << bitnum);
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}
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static int notmine(int num, int *bank, int *bitnum)
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{
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if (bad_arg(num, bank, bitnum))
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return -1;
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return !(lock[*bank] & (1UL << *bitnum));
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}
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static int gpio_init(void)
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{
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u8 tmpbyte;
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u16 tmpword;
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u32 tmplong;
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/* Have we already done this? */
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if (found_it_once)
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return 0;
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/* Where should it be? */
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dev = PCI_BDF(0, 0x1f, 0);
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/* Is the device present? */
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pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword);
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if (tmpword != PCI_VENDOR_ID_INTEL) {
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debug("%s: wrong VendorID\n", __func__);
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return -1;
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}
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pci_read_config_word(dev, PCI_DEVICE_ID, &tmpword);
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debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
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/*
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* We'd like to validate the Device ID too, but pretty much any
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* value is either a) correct with slight differences, or b)
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* correct but undocumented. We'll have to check a bunch of other
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* things instead...
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*/
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/* I/O should already be enabled (it's a RO bit). */
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pci_read_config_word(dev, PCI_COMMAND, &tmpword);
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if (!(tmpword & PCI_COMMAND_IO)) {
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debug("%s: device IO not enabled\n", __func__);
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return -1;
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}
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/* Header Type must be normal (bits 6-0 only; see spec.) */
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte);
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if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
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debug("%s: invalid Header type\n", __func__);
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return -1;
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}
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/* Base Class must be a bridge device */
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pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte);
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if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
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debug("%s: invalid class\n", __func__);
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return -1;
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}
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/* Sub Class must be ISA */
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pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte);
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if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
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debug("%s: invalid subclass\n", __func__);
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return -1;
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}
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/* Programming Interface must be 0x00 (no others exist) */
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pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte);
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if (tmpbyte != 0x00) {
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debug("%s: invalid interface type\n", __func__);
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return -1;
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}
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/*
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* GPIOBASE moved to its current offset with ICH6, but prior to
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* that it was unused (or undocumented). Check that it looks
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* okay: not all ones or zeros, and mapped to I/O space (bit 0).
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*/
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pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong);
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if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
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!(tmplong & 0x00000001)) {
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debug("%s: unexpected GPIOBASE value\n", __func__);
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return -1;
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}
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/*
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* Okay, I guess we're looking at the right device. The actual
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* GPIO registers are in the PCI device's I/O space, starting
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* at the offset that we just read. Bit 0 indicates that it's
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* an I/O address, not a memory address, so mask that off.
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*/
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gpiobase = tmplong & 0xfffffffe;
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/* Finally. These are the droids we're looking for. */
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found_it_once = 1;
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return 0;
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}
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int gpio_request(unsigned num, const char *label /* UNUSED */)
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{
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u32 tmplong;
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int i = 0, j = 0;
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/* Is the hardware ready? */
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if (gpio_init())
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return -1;
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if (bad_arg(num, &i, &j))
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return -1;
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/*
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* Make sure that the GPIO pin we want isn't already in use for some
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* built-in hardware function. We have to check this for every
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* requested pin.
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*/
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tmplong = inl(gpiobase + gpio_bank[i].use_sel);
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if (!(tmplong & (1UL << j))) {
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debug("%s: gpio %d is reserved for internal use\n", __func__,
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num);
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return -1;
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}
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return mark_gpio(i, j);
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}
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int gpio_free(unsigned num)
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{
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int i = 0, j = 0;
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if (notmine(num, &i, &j))
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return -1;
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clear_gpio(i, j);
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return 0;
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}
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int gpio_direction_input(unsigned num)
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{
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u32 tmplong;
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int i = 0, j = 0;
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if (notmine(num, &i, &j))
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return -1;
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tmplong = inl(gpiobase + gpio_bank[i].io_sel);
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tmplong |= (1UL << j);
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outl(gpiobase + gpio_bank[i].io_sel, tmplong);
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return 0;
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}
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int gpio_direction_output(unsigned num, int value)
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{
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u32 tmplong;
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int i = 0, j = 0;
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if (notmine(num, &i, &j))
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return -1;
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tmplong = inl(gpiobase + gpio_bank[i].io_sel);
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tmplong &= ~(1UL << j);
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outl(gpiobase + gpio_bank[i].io_sel, tmplong);
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return 0;
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}
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int gpio_get_value(unsigned num)
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{
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u32 tmplong;
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int i = 0, j = 0;
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int r;
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if (notmine(num, &i, &j))
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return -1;
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tmplong = inl(gpiobase + gpio_bank[i].lvl);
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r = (tmplong & (1UL << j)) ? 1 : 0;
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return r;
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}
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int gpio_set_value(unsigned num, int value)
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{
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u32 tmplong;
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int i = 0, j = 0;
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if (notmine(num, &i, &j))
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return -1;
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tmplong = inl(gpiobase + gpio_bank[i].lvl);
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if (value)
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tmplong |= (1UL << j);
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else
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tmplong &= ~(1UL << j);
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outl(gpiobase + gpio_bank[i].lvl, tmplong);
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return 0;
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}
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