67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mvmfp.h>
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#include <asm/arch/mfp.h>
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/*
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* mfp_config
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*
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* On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
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* configuration registers to configure each GPIO/Function pin on the
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* SoC.
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*
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* This function reads the array of values for
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* MFPR_X registers and programms them into respective
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* Multi-Function Pin registers.
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* It supports - Alternate Function Selection programming.
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*
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* Whereas,
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* The Configureation value is constructed using MFP()
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* array consists of 32bit values as defined in MFP(xx,xx..) macro
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*/
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void mfp_config(u32 *mfp_cfgs)
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{
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u32 *p_mfpr = NULL;
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u32 cfg_val, val;
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do {
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cfg_val = *mfp_cfgs++;
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/* exit if End of configuration table detected */
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if (cfg_val == MFP_EOC)
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break;
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p_mfpr = (u32 *)(MV_MFPR_BASE
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+ MFP_REG_GET_OFFSET(cfg_val));
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/* Write a mfg register as per configuration */
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val = 0;
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if (cfg_val & MFP_AF_FLAG)
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/* Abstract and program Afternate-Func Selection */
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val |= cfg_val & MFP_AF_MASK;
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if (cfg_val & MFP_EDGE_FLAG)
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/* Abstract and program Edge configuration */
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val |= cfg_val & MFP_LPM_EDGE_MASK;
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if (cfg_val & MFP_DRIVE_FLAG)
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/* Abstract and program Drive configuration */
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val |= cfg_val & MFP_DRIVE_MASK;
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if (cfg_val & MFP_PULL_FLAG)
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/* Abstract and program Pullup/down configuration */
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val |= cfg_val & MFP_PULL_MASK;
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writel(val, p_mfpr);
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} while (1);
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/*
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* perform a read-back of any MFPR register to make sure the
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* previous writings are finished
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*/
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readl(p_mfpr);
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}
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