872 lines
20 KiB
C
872 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include "ddr_ml_wrapper.h"
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#include "ddr3_training_ip_flow.h"
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#include "mv_ddr_topology.h"
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#include "mv_ddr_training_db.h"
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#include "ddr3_training_ip_db.h"
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/* Device attributes structures */
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enum mv_ddr_dev_attribute ddr_dev_attributes[MV_ATTR_LAST];
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int ddr_dev_attr_init_done = 0;
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static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index);
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static inline u32 pattern_table_get_sso_word(u8 sso, u8 index);
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static inline u32 pattern_table_get_vref_word(u8 index);
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static inline u32 pattern_table_get_vref_word16(u8 index);
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static inline u32 pattern_table_get_sso_full_xtalk_word(u8 bit, u8 index);
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static inline u32 pattern_table_get_sso_full_xtalk_word16(u8 bit, u8 index);
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static inline u32 pattern_table_get_sso_xtalk_free_word(u8 bit, u8 index);
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static inline u32 pattern_table_get_sso_xtalk_free_word16(u8 bit, u8 index);
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static inline u32 pattern_table_get_isi_word(u8 index);
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static inline u32 pattern_table_get_isi_word16(u8 index);
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/* List of allowed frequency listed in order of enum mv_ddr_freq */
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static unsigned int freq_val[MV_DDR_FREQ_LAST] = {
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0, /*MV_DDR_FREQ_LOW_FREQ */
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400, /*MV_DDR_FREQ_400, */
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533, /*MV_DDR_FREQ_533, */
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666, /*MV_DDR_FREQ_667, */
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800, /*MV_DDR_FREQ_800, */
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933, /*MV_DDR_FREQ_933, */
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1066, /*MV_DDR_FREQ_1066, */
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311, /*MV_DDR_FREQ_311, */
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333, /*MV_DDR_FREQ_333, */
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467, /*MV_DDR_FREQ_467, */
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850, /*MV_DDR_FREQ_850, */
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600, /*MV_DDR_FREQ_600 */
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300, /*MV_DDR_FREQ_300 */
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900, /*MV_DDR_FREQ_900 */
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360, /*MV_DDR_FREQ_360 */
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1000 /*MV_DDR_FREQ_1000 */
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};
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unsigned int *mv_ddr_freq_tbl_get(void)
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{
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return &freq_val[0];
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}
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u32 mv_ddr_freq_get(enum mv_ddr_freq freq)
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{
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return freq_val[freq];
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}
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/* cas latency values per frequency for each speed bin index */
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static struct mv_ddr_cl_val_per_freq cl_table[] = {
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/*
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* 400M 667M 933M 311M 467M 600M 360
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* 100M 533M 800M 1066M 333M 850M 900
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* 1000 (the order is 100, 400, 533 etc.)
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*/
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/* DDR3-800D */
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{ {6, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
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/* DDR3-800E */
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{ {6, 6, 0, 0, 0, 0, 0, 6, 6, 0, 0, 0, 6, 0, 6, 0} },
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/* DDR3-1066E */
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{ {6, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 0, 5, 0, 5, 0} },
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/* DDR3-1066F */
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{ {6, 6, 7, 0, 0, 0, 0, 6, 6, 7, 0, 0, 6, 0, 6, 0} },
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/* DDR3-1066G */
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{ {6, 6, 8, 0, 0, 0, 0, 6, 6, 8, 0, 0, 6, 0, 6, 0} },
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/* DDR3-1333F* */
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{ {6, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333G */
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{ {6, 5, 7, 8, 0, 0, 0, 5, 5, 7, 0, 8, 5, 0, 5, 0} },
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/* DDR3-1333H */
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{ {6, 6, 8, 9, 0, 0, 0, 6, 6, 8, 0, 9, 6, 0, 6, 0} },
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/* DDR3-1333J* */
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{ {6, 6, 8, 10, 0, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0}
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/* DDR3-1600G* */},
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{ {6, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600H */
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{ {6, 5, 6, 8, 9, 0, 0, 5, 5, 6, 0, 8, 5, 0, 5, 0} },
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/* DDR3-1600J */
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{ {6, 5, 7, 9, 10, 0, 0, 5, 5, 7, 0, 9, 5, 0, 5, 0} },
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/* DDR3-1600K */
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{ {6, 6, 8, 10, 11, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0 } },
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/* DDR3-1866J* */
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{ {6, 5, 6, 8, 9, 11, 0, 5, 5, 6, 11, 8, 5, 0, 5, 0} },
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/* DDR3-1866K */
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{ {6, 5, 7, 8, 10, 11, 0, 5, 5, 7, 11, 8, 5, 11, 5, 11} },
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/* DDR3-1866L */
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{ {6, 6, 7, 9, 11, 12, 0, 6, 6, 7, 12, 9, 6, 12, 6, 12} },
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/* DDR3-1866M* */
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{ {6, 6, 8, 10, 11, 13, 0, 6, 6, 8, 13, 10, 6, 13, 6, 13} },
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/* DDR3-2133K* */
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{ {6, 5, 6, 7, 9, 10, 11, 5, 5, 6, 10, 7, 5, 11, 5, 11} },
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/* DDR3-2133L */
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{ {6, 5, 6, 8, 9, 11, 12, 5, 5, 6, 11, 8, 5, 12, 5, 12} },
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/* DDR3-2133M */
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{ {6, 5, 7, 9, 10, 12, 13, 5, 5, 7, 12, 9, 5, 13, 5, 13} },
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/* DDR3-2133N* */
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{ {6, 6, 7, 9, 11, 13, 14, 6, 6, 7, 13, 9, 6, 14, 6, 14} },
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/* DDR3-1333H-ext */
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{ {6, 6, 7, 9, 0, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
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/* DDR3-1600K-ext */
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{ {6, 6, 7, 9, 11, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
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/* DDR3-1866M-ext */
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{ {6, 6, 7, 9, 11, 13, 0, 6, 6, 7, 13, 9, 6, 13, 6, 13} },
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};
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u32 mv_ddr_cl_val_get(u32 index, u32 freq)
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{
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return cl_table[index].cl_val[freq];
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}
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/* cas write latency values per frequency for each speed bin index */
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static struct mv_ddr_cl_val_per_freq cwl_table[] = {
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/*
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* 400M 667M 933M 311M 467M 600M 360
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* 100M 533M 800M 1066M 333M 850M 900
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* (the order is 100, 400, 533 etc.)
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*/
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/* DDR3-800D */
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{ {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
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/* DDR3-800E */
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{ {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
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/* DDR3-1066E */
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{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1066F */
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{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1066G */
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{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333F* */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333G */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333H */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1333J* */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600G* */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600H */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600J */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600K */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1866J* */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
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/* DDR3-1866K */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
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/* DDR3-1866L */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
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/* DDR3-1866M* */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
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/* DDR3-2133K* */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-2133L */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-2133M */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-2133N* */
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{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
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/* DDR3-1333H-ext */
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{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1600K-ext */
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{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
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/* DDR3-1866M-ext */
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{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
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};
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u32 mv_ddr_cwl_val_get(u32 index, u32 freq)
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{
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return cwl_table[index].cl_val[freq];
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}
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u8 twr_mask_table[] = {
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10,
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10,
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10,
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10,
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10,
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1, /* 5 */
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2, /* 6 */
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3, /* 7 */
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4, /* 8 */
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10,
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5, /* 10 */
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10,
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6, /* 12 */
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10,
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7, /* 14 */
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10,
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0 /* 16 */
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};
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u8 cl_mask_table[] = {
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0,
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0,
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0,
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0,
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0,
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0x2,
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0x4,
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0x6,
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0x8,
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0xa,
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0xc,
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0xe,
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0x1,
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0x3,
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0x5,
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0x5
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};
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u8 cwl_mask_table[] = {
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0,
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0,
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0,
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0,
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0,
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0,
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0x1,
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0x2,
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0x3,
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0x4,
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0x5,
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0x6,
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0x7,
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0x8,
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0x9,
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0x9
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};
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/* RFC values (in ns) */
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static unsigned int rfc_table[] = {
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90, /* 512M */
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110, /* 1G */
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160, /* 2G */
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260, /* 4G */
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350, /* 8G */
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0, /* TODO: placeholder for 16-Mbit dev width */
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0, /* TODO: placeholder for 32-Mbit dev width */
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0, /* TODO: placeholder for 12-Mbit dev width */
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0 /* TODO: placeholder for 24-Mbit dev width */
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};
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u32 mv_ddr_rfc_get(u32 mem)
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{
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return rfc_table[mem];
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}
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u32 speed_bin_table_t_rc[] = {
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50000,
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52500,
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48750,
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50625,
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52500,
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46500,
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48000,
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49500,
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51000,
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45000,
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46250,
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47500,
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48750,
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44700,
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45770,
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46840,
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47910,
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43285,
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44220,
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45155,
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46090
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};
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u32 speed_bin_table_t_rcd_t_rp[] = {
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12500,
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15000,
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11250,
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13125,
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15000,
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10500,
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12000,
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13500,
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15000,
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10000,
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11250,
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12500,
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13750,
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10700,
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11770,
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12840,
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13910,
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10285,
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11220,
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12155,
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13090,
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};
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enum {
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PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR = 0,
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PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM
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};
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static u8 pattern_killer_pattern_table_map[KILLER_PATTERN_LENGTH * 2][2] = {
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/*Aggressor / Victim */
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{1, 0},
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{0, 0},
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{1, 0},
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{1, 1},
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{0, 1},
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{0, 1},
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{1, 0},
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{0, 1},
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{1, 0},
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{0, 1},
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{1, 0},
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{1, 0},
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{0, 1},
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{1, 0},
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{0, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{1, 0},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{0, 0},
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{0, 0},
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{0, 1},
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{0, 1},
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{1, 1},
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{0, 0},
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{0, 0},
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{1, 1},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{1, 1},
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{0, 0},
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{0, 0},
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{1, 1},
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{0, 0},
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{1, 1},
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{0, 1},
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{0, 0},
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{0, 1},
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{0, 1},
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{0, 0},
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{1, 1},
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{1, 1},
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{1, 0},
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{1, 0},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1},
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{1, 1}
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};
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static u8 pattern_vref_pattern_table_map[] = {
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/* 1 means 0xffffffff, 0 is 0x0 */
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0xb8,
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0x52,
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0x55,
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0x8a,
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0x33,
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0xa6,
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0x6d,
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0xfe
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};
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static struct mv_ddr_page_element page_tbl[] = {
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/* 8-bit, 16-bit page size */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 512M */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 1G */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 2G */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 4G */
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{MV_DDR_PAGE_SIZE_2K, MV_DDR_PAGE_SIZE_2K}, /* 8G */
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{0, 0}, /* TODO: placeholder for 16-Mbit die capacity */
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{0, 0}, /* TODO: placeholder for 32-Mbit die capacity */
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{0, 0}, /* TODO: placeholder for 12-Mbit die capacity */
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{0, 0} /* TODO: placeholder for 24-Mbit die capacity */
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};
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u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size)
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{
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if (bus_width == MV_DDR_DEV_WIDTH_8BIT)
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return page_tbl[mem_size].page_size_8bit;
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else
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return page_tbl[mem_size].page_size_16bit;
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}
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/* Return speed Bin value for selected index and t* element */
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unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element)
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{
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u32 result = 0;
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switch (element) {
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case SPEED_BIN_TRCD:
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case SPEED_BIN_TRP:
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result = speed_bin_table_t_rcd_t_rp[index];
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break;
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case SPEED_BIN_TRAS:
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if (index <= SPEED_BIN_DDR_1066G)
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result = 37500;
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else if (index <= SPEED_BIN_DDR_1333J)
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result = 36000;
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else if (index <= SPEED_BIN_DDR_1600K)
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result = 35000;
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else if (index <= SPEED_BIN_DDR_1866M)
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result = 34000;
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else
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result = 33000;
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break;
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case SPEED_BIN_TRC:
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result = speed_bin_table_t_rc[index];
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break;
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case SPEED_BIN_TRRD1K:
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if (index <= SPEED_BIN_DDR_800E)
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result = 10000;
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else if (index <= SPEED_BIN_DDR_1066G)
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result = 7500;
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else if (index <= SPEED_BIN_DDR_1600K)
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result = 6000;
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else
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result = 5000;
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break;
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case SPEED_BIN_TRRD2K:
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if (index <= SPEED_BIN_DDR_1066G)
|
|
result = 10000;
|
|
else if (index <= SPEED_BIN_DDR_1600K)
|
|
result = 7500;
|
|
else
|
|
result = 6000;
|
|
break;
|
|
case SPEED_BIN_TPD:
|
|
if (index < SPEED_BIN_DDR_800E)
|
|
result = 7500;
|
|
else if (index < SPEED_BIN_DDR_1333J)
|
|
result = 5625;
|
|
else
|
|
result = 5000;
|
|
break;
|
|
case SPEED_BIN_TFAW1K:
|
|
if (index <= SPEED_BIN_DDR_800E)
|
|
result = 40000;
|
|
else if (index <= SPEED_BIN_DDR_1066G)
|
|
result = 37500;
|
|
else if (index <= SPEED_BIN_DDR_1600K)
|
|
result = 30000;
|
|
else if (index <= SPEED_BIN_DDR_1866M)
|
|
result = 27000;
|
|
else
|
|
result = 25000;
|
|
break;
|
|
case SPEED_BIN_TFAW2K:
|
|
if (index <= SPEED_BIN_DDR_1066G)
|
|
result = 50000;
|
|
else if (index <= SPEED_BIN_DDR_1333J)
|
|
result = 45000;
|
|
else if (index <= SPEED_BIN_DDR_1600K)
|
|
result = 40000;
|
|
else
|
|
result = 35000;
|
|
break;
|
|
case SPEED_BIN_TWTR:
|
|
result = 7500;
|
|
break;
|
|
case SPEED_BIN_TRTP:
|
|
result = 7500;
|
|
break;
|
|
case SPEED_BIN_TWR:
|
|
result = 15000;
|
|
break;
|
|
case SPEED_BIN_TMOD:
|
|
result = 15000;
|
|
break;
|
|
case SPEED_BIN_TXPDLL:
|
|
result = 24000;
|
|
break;
|
|
case SPEED_BIN_TXSDLL:
|
|
result = 512;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_killer_word(u8 dqs, u8 index)
|
|
{
|
|
u8 i, byte = 0;
|
|
u8 role;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
role = (i == dqs) ?
|
|
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
|
|
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
|
|
byte |= pattern_killer_pattern_table_map[index][role] << i;
|
|
}
|
|
|
|
return byte | (byte << 8) | (byte << 16) | (byte << 24);
|
|
}
|
|
|
|
static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index)
|
|
{
|
|
u8 i, byte0 = 0, byte1 = 0;
|
|
u8 role;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
role = (i == dqs) ?
|
|
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
|
|
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
|
|
byte0 |= pattern_killer_pattern_table_map[index * 2][role] << i;
|
|
byte1 |= pattern_killer_pattern_table_map[index * 2 + 1][role] << i;
|
|
}
|
|
|
|
return byte0 | (byte0 << 8) | (byte1 << 16) | (byte1 << 24);
|
|
}
|
|
|
|
static inline u32 pattern_table_get_sso_word(u8 sso, u8 index)
|
|
{
|
|
u8 step = sso + 1;
|
|
|
|
if (0 == ((index / step) & 1))
|
|
return 0x0;
|
|
else
|
|
return 0xffffffff;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_sso_full_xtalk_word(u8 bit, u8 index)
|
|
{
|
|
u8 byte = (1 << bit);
|
|
|
|
if ((index & 1) == 1)
|
|
byte = ~byte;
|
|
|
|
return byte | (byte << 8) | (byte << 16) | (byte << 24);
|
|
|
|
}
|
|
|
|
static inline u32 pattern_table_get_sso_xtalk_free_word(u8 bit, u8 index)
|
|
{
|
|
u8 byte = (1 << bit);
|
|
|
|
if ((index & 1) == 1)
|
|
byte = 0;
|
|
|
|
return byte | (byte << 8) | (byte << 16) | (byte << 24);
|
|
}
|
|
|
|
static inline u32 pattern_table_get_isi_word(u8 index)
|
|
{
|
|
u8 i0 = index % 32;
|
|
u8 i1 = index % 8;
|
|
u32 word;
|
|
|
|
if (i0 > 15)
|
|
word = ((i1 == 5) | (i1 == 7)) ? 0xffffffff : 0x0;
|
|
else
|
|
word = (i1 == 6) ? 0xffffffff : 0x0;
|
|
|
|
word = ((i0 % 16) > 7) ? ~word : word;
|
|
|
|
return word;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_sso_full_xtalk_word16(u8 bit, u8 index)
|
|
{
|
|
u8 byte = (1 << bit);
|
|
|
|
if ((index & 1) == 1)
|
|
byte = ~byte;
|
|
|
|
return byte | (byte << 8) | ((~byte) << 16) | ((~byte) << 24);
|
|
}
|
|
|
|
static inline u32 pattern_table_get_sso_xtalk_free_word16(u8 bit, u8 index)
|
|
{
|
|
u8 byte = (1 << bit);
|
|
|
|
if ((index & 1) == 0)
|
|
return (byte << 16) | (byte << 24);
|
|
else
|
|
return byte | (byte << 8);
|
|
}
|
|
|
|
static inline u32 pattern_table_get_isi_word16(u8 index)
|
|
{
|
|
u8 i0 = index % 16;
|
|
u8 i1 = index % 4;
|
|
u32 word;
|
|
|
|
if (i0 > 7)
|
|
word = (i1 > 1) ? 0x0000ffff : 0x0;
|
|
else
|
|
word = (i1 == 3) ? 0xffff0000 : 0x0;
|
|
|
|
word = ((i0 % 8) > 3) ? ~word : word;
|
|
|
|
return word;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_vref_word(u8 index)
|
|
{
|
|
if (0 == ((pattern_vref_pattern_table_map[index / 8] >>
|
|
(index % 8)) & 1))
|
|
return 0x0;
|
|
else
|
|
return 0xffffffff;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_vref_word16(u8 index)
|
|
{
|
|
if (0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
|
|
0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
|
|
return 0x00000000;
|
|
else if (1 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
|
|
0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
|
|
return 0xffff0000;
|
|
else if (0 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
|
|
1 == pattern_killer_pattern_table_map
|
|
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
|
|
return 0x0000ffff;
|
|
else
|
|
return 0xffffffff;
|
|
}
|
|
|
|
static inline u32 pattern_table_get_static_pbs_word(u8 index)
|
|
{
|
|
u16 temp;
|
|
|
|
temp = ((0x00ff << (index / 3)) & 0xff00) >> 8;
|
|
|
|
return temp | (temp << 8) | (temp << 16) | (temp << 24);
|
|
}
|
|
|
|
u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
|
|
{
|
|
u32 pattern = 0;
|
|
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
|
|
|
|
if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) {
|
|
/* 32/64-bit patterns */
|
|
switch (type) {
|
|
case PATTERN_PBS1:
|
|
case PATTERN_PBS2:
|
|
if (index == 0 || index == 2 || index == 5 ||
|
|
index == 7)
|
|
pattern = PATTERN_55;
|
|
else
|
|
pattern = PATTERN_AA;
|
|
break;
|
|
case PATTERN_PBS3:
|
|
if (0 == (index & 1))
|
|
pattern = PATTERN_55;
|
|
else
|
|
pattern = PATTERN_AA;
|
|
break;
|
|
case PATTERN_RL:
|
|
if (index < 6)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_80;
|
|
break;
|
|
case PATTERN_STATIC_PBS:
|
|
pattern = pattern_table_get_static_pbs_word(index);
|
|
break;
|
|
case PATTERN_KILLER_DQ0:
|
|
case PATTERN_KILLER_DQ1:
|
|
case PATTERN_KILLER_DQ2:
|
|
case PATTERN_KILLER_DQ3:
|
|
case PATTERN_KILLER_DQ4:
|
|
case PATTERN_KILLER_DQ5:
|
|
case PATTERN_KILLER_DQ6:
|
|
case PATTERN_KILLER_DQ7:
|
|
pattern = pattern_table_get_killer_word(
|
|
(u8)(type - PATTERN_KILLER_DQ0), index);
|
|
break;
|
|
case PATTERN_RL2:
|
|
if (index < 6)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_01;
|
|
break;
|
|
case PATTERN_TEST:
|
|
if (index > 1 && index < 6)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_FF;
|
|
break;
|
|
case PATTERN_FULL_SSO0:
|
|
case PATTERN_FULL_SSO1:
|
|
case PATTERN_FULL_SSO2:
|
|
case PATTERN_FULL_SSO3:
|
|
pattern = pattern_table_get_sso_word(
|
|
(u8)(type - PATTERN_FULL_SSO0), index);
|
|
break;
|
|
case PATTERN_VREF:
|
|
pattern = pattern_table_get_vref_word(index);
|
|
break;
|
|
case PATTERN_SSO_FULL_XTALK_DQ0:
|
|
case PATTERN_SSO_FULL_XTALK_DQ1:
|
|
case PATTERN_SSO_FULL_XTALK_DQ2:
|
|
case PATTERN_SSO_FULL_XTALK_DQ3:
|
|
case PATTERN_SSO_FULL_XTALK_DQ4:
|
|
case PATTERN_SSO_FULL_XTALK_DQ5:
|
|
case PATTERN_SSO_FULL_XTALK_DQ6:
|
|
case PATTERN_SSO_FULL_XTALK_DQ7:
|
|
pattern = pattern_table_get_sso_full_xtalk_word(
|
|
(u8)(type - PATTERN_SSO_FULL_XTALK_DQ0), index);
|
|
break;
|
|
case PATTERN_SSO_XTALK_FREE_DQ0:
|
|
case PATTERN_SSO_XTALK_FREE_DQ1:
|
|
case PATTERN_SSO_XTALK_FREE_DQ2:
|
|
case PATTERN_SSO_XTALK_FREE_DQ3:
|
|
case PATTERN_SSO_XTALK_FREE_DQ4:
|
|
case PATTERN_SSO_XTALK_FREE_DQ5:
|
|
case PATTERN_SSO_XTALK_FREE_DQ6:
|
|
case PATTERN_SSO_XTALK_FREE_DQ7:
|
|
pattern = pattern_table_get_sso_xtalk_free_word(
|
|
(u8)(type - PATTERN_SSO_XTALK_FREE_DQ0), index);
|
|
break;
|
|
case PATTERN_ISI_XTALK_FREE:
|
|
pattern = pattern_table_get_isi_word(index);
|
|
break;
|
|
default:
|
|
printf("error: %s: unsupported pattern type [%d] found\n",
|
|
__func__, (int)type);
|
|
pattern = 0;
|
|
break;
|
|
}
|
|
} else {
|
|
/* 16bit patterns */
|
|
switch (type) {
|
|
case PATTERN_PBS1:
|
|
case PATTERN_PBS2:
|
|
case PATTERN_PBS3:
|
|
pattern = PATTERN_55AA;
|
|
break;
|
|
case PATTERN_RL:
|
|
if (index < 3)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_80;
|
|
break;
|
|
case PATTERN_STATIC_PBS:
|
|
pattern = PATTERN_00FF;
|
|
break;
|
|
case PATTERN_KILLER_DQ0:
|
|
case PATTERN_KILLER_DQ1:
|
|
case PATTERN_KILLER_DQ2:
|
|
case PATTERN_KILLER_DQ3:
|
|
case PATTERN_KILLER_DQ4:
|
|
case PATTERN_KILLER_DQ5:
|
|
case PATTERN_KILLER_DQ6:
|
|
case PATTERN_KILLER_DQ7:
|
|
pattern = pattern_table_get_killer_word16(
|
|
(u8)(type - PATTERN_KILLER_DQ0), index);
|
|
break;
|
|
case PATTERN_RL2:
|
|
if (index < 3)
|
|
pattern = PATTERN_00;
|
|
else
|
|
pattern = PATTERN_01;
|
|
break;
|
|
case PATTERN_TEST:
|
|
if ((index == 0) || (index == 3))
|
|
pattern = 0x00000000;
|
|
else
|
|
pattern = 0xFFFFFFFF;
|
|
break;
|
|
case PATTERN_FULL_SSO0:
|
|
pattern = 0x0000ffff;
|
|
break;
|
|
case PATTERN_FULL_SSO1:
|
|
case PATTERN_FULL_SSO2:
|
|
case PATTERN_FULL_SSO3:
|
|
pattern = pattern_table_get_sso_word(
|
|
(u8)(type - PATTERN_FULL_SSO1), index);
|
|
break;
|
|
case PATTERN_VREF:
|
|
pattern = pattern_table_get_vref_word16(index);
|
|
break;
|
|
case PATTERN_SSO_FULL_XTALK_DQ0:
|
|
case PATTERN_SSO_FULL_XTALK_DQ1:
|
|
case PATTERN_SSO_FULL_XTALK_DQ2:
|
|
case PATTERN_SSO_FULL_XTALK_DQ3:
|
|
case PATTERN_SSO_FULL_XTALK_DQ4:
|
|
case PATTERN_SSO_FULL_XTALK_DQ5:
|
|
case PATTERN_SSO_FULL_XTALK_DQ6:
|
|
case PATTERN_SSO_FULL_XTALK_DQ7:
|
|
pattern = pattern_table_get_sso_full_xtalk_word16(
|
|
(u8)(type - PATTERN_SSO_FULL_XTALK_DQ0), index);
|
|
break;
|
|
case PATTERN_SSO_XTALK_FREE_DQ0:
|
|
case PATTERN_SSO_XTALK_FREE_DQ1:
|
|
case PATTERN_SSO_XTALK_FREE_DQ2:
|
|
case PATTERN_SSO_XTALK_FREE_DQ3:
|
|
case PATTERN_SSO_XTALK_FREE_DQ4:
|
|
case PATTERN_SSO_XTALK_FREE_DQ5:
|
|
case PATTERN_SSO_XTALK_FREE_DQ6:
|
|
case PATTERN_SSO_XTALK_FREE_DQ7:
|
|
pattern = pattern_table_get_sso_xtalk_free_word16(
|
|
(u8)(type - PATTERN_SSO_XTALK_FREE_DQ0), index);
|
|
break;
|
|
case PATTERN_ISI_XTALK_FREE:
|
|
pattern = pattern_table_get_isi_word16(index);
|
|
break;
|
|
default:
|
|
printf("error: %s: unsupported pattern type [%d] found\n",
|
|
__func__, (int)type);
|
|
pattern = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return pattern;
|
|
}
|
|
|
|
/* Device attribute functions */
|
|
void ddr3_tip_dev_attr_init(u32 dev_num)
|
|
{
|
|
u32 attr_id;
|
|
|
|
for (attr_id = 0; attr_id < MV_ATTR_LAST; attr_id++)
|
|
ddr_dev_attributes[attr_id] = 0xFF;
|
|
|
|
ddr_dev_attr_init_done = 1;
|
|
}
|
|
|
|
u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id)
|
|
{
|
|
if (ddr_dev_attr_init_done == 0)
|
|
ddr3_tip_dev_attr_init(dev_num);
|
|
|
|
return ddr_dev_attributes[attr_id];
|
|
}
|
|
|
|
void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value)
|
|
{
|
|
if (ddr_dev_attr_init_done == 0)
|
|
ddr3_tip_dev_attr_init(dev_num);
|
|
|
|
ddr_dev_attributes[attr_id] = value;
|
|
}
|