405 lines
9.9 KiB
C
405 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _MV_DDR_TOPOLOGY_H
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#define _MV_DDR_TOPOLOGY_H
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#define MAX_CS_NUM 4
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#if defined(CONFIG_DDR4)
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enum mv_ddr_speed_bin {
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SPEED_BIN_DDR_1600J,
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SPEED_BIN_DDR_1600K,
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SPEED_BIN_DDR_1600L,
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SPEED_BIN_DDR_1866L,
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SPEED_BIN_DDR_1866M,
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SPEED_BIN_DDR_1866N,
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SPEED_BIN_DDR_2133N,
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SPEED_BIN_DDR_2133P,
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SPEED_BIN_DDR_2133R,
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SPEED_BIN_DDR_2400P,
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SPEED_BIN_DDR_2400R,
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SPEED_BIN_DDR_2400T,
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SPEED_BIN_DDR_2400U,
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SPEED_BIN_DDR_2666T,
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SPEED_BIN_DDR_2666U,
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SPEED_BIN_DDR_2666V,
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SPEED_BIN_DDR_2666W,
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SPEED_BIN_DDR_2933V,
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SPEED_BIN_DDR_2933W,
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SPEED_BIN_DDR_2933Y,
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SPEED_BIN_DDR_2933AA,
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SPEED_BIN_DDR_3200W,
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SPEED_BIN_DDR_3200AA,
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SPEED_BIN_DDR_3200AC
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};
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enum mv_ddr_freq {
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MV_DDR_FREQ_LOW_FREQ,
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MV_DDR_FREQ_650,
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MV_DDR_FREQ_667,
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MV_DDR_FREQ_800,
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MV_DDR_FREQ_933,
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MV_DDR_FREQ_1066,
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MV_DDR_FREQ_900,
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MV_DDR_FREQ_1000,
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MV_DDR_FREQ_1050,
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MV_DDR_FREQ_1200,
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MV_DDR_FREQ_1333,
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MV_DDR_FREQ_1466,
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MV_DDR_FREQ_1600,
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MV_DDR_FREQ_LAST,
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MV_DDR_FREQ_SAR
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};
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enum mv_ddr_speed_bin_timing {
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SPEED_BIN_TRCD,
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SPEED_BIN_TRP,
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SPEED_BIN_TRAS,
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SPEED_BIN_TRC,
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SPEED_BIN_TRRD0_5K,
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SPEED_BIN_TRRD1K,
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SPEED_BIN_TRRD2K,
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SPEED_BIN_TRRDL0_5K,
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SPEED_BIN_TRRDL1K,
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SPEED_BIN_TRRDL2K,
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SPEED_BIN_TPD,
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SPEED_BIN_TFAW0_5K,
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SPEED_BIN_TFAW1K,
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SPEED_BIN_TFAW2K,
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SPEED_BIN_TWTR,
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SPEED_BIN_TWTRL,
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SPEED_BIN_TRTP,
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SPEED_BIN_TWR,
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SPEED_BIN_TMOD,
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SPEED_BIN_TXPDLL,
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SPEED_BIN_TXSDLL,
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SPEED_BIN_TCCDL
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};
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#else /* CONFIG_DDR3 */
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enum mv_ddr_speed_bin {
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SPEED_BIN_DDR_800D,
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SPEED_BIN_DDR_800E,
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SPEED_BIN_DDR_1066E,
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SPEED_BIN_DDR_1066F,
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SPEED_BIN_DDR_1066G,
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SPEED_BIN_DDR_1333F,
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SPEED_BIN_DDR_1333G,
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SPEED_BIN_DDR_1333H,
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SPEED_BIN_DDR_1333J,
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SPEED_BIN_DDR_1600G,
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SPEED_BIN_DDR_1600H,
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SPEED_BIN_DDR_1600J,
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SPEED_BIN_DDR_1600K,
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SPEED_BIN_DDR_1866J,
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SPEED_BIN_DDR_1866K,
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SPEED_BIN_DDR_1866L,
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SPEED_BIN_DDR_1866M,
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SPEED_BIN_DDR_2133K,
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SPEED_BIN_DDR_2133L,
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SPEED_BIN_DDR_2133M,
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SPEED_BIN_DDR_2133N,
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SPEED_BIN_DDR_1333H_EXT,
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SPEED_BIN_DDR_1600K_EXT,
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SPEED_BIN_DDR_1866M_EXT
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};
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enum mv_ddr_freq {
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MV_DDR_FREQ_LOW_FREQ,
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MV_DDR_FREQ_400,
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MV_DDR_FREQ_533,
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MV_DDR_FREQ_667,
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MV_DDR_FREQ_800,
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MV_DDR_FREQ_933,
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MV_DDR_FREQ_1066,
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MV_DDR_FREQ_311,
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MV_DDR_FREQ_333,
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MV_DDR_FREQ_467,
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MV_DDR_FREQ_850,
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MV_DDR_FREQ_600,
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MV_DDR_FREQ_300,
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MV_DDR_FREQ_900,
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MV_DDR_FREQ_360,
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MV_DDR_FREQ_1000,
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MV_DDR_FREQ_LAST,
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MV_DDR_FREQ_SAR
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};
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enum mv_ddr_speed_bin_timing {
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SPEED_BIN_TRCD,
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SPEED_BIN_TRP,
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SPEED_BIN_TRAS,
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SPEED_BIN_TRC,
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SPEED_BIN_TRRD1K,
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SPEED_BIN_TRRD2K,
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SPEED_BIN_TPD,
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SPEED_BIN_TFAW1K,
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SPEED_BIN_TFAW2K,
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SPEED_BIN_TWTR,
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SPEED_BIN_TRTP,
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SPEED_BIN_TWR,
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SPEED_BIN_TMOD,
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SPEED_BIN_TXPDLL,
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SPEED_BIN_TXSDLL
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};
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#endif /* CONFIG_DDR4 */
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/* ddr bus masks */
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#define BUS_MASK_32BIT 0xf
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#define BUS_MASK_32BIT_ECC 0x1f
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#define BUS_MASK_16BIT 0x3
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#define BUS_MASK_16BIT_ECC 0x13
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#define BUS_MASK_16BIT_ECC_PUP3 0xb
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#define MV_DDR_64BIT_BUS_MASK 0xff
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#define MV_DDR_64BIT_ECC_PUP8_BUS_MASK 0x1ff
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#define MV_DDR_32BIT_ECC_PUP8_BUS_MASK 0x10f
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#define MV_DDR_CS_BITMASK_1CS 0x1
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#define MV_DDR_CS_BITMASK_2CS 0x3
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#define MV_DDR_ONE_SPHY_PER_DUNIT 1
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#define MV_DDR_TWO_SPHY_PER_DUNIT 2
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/* source of ddr configuration data */
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enum mv_ddr_cfg_src {
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MV_DDR_CFG_DEFAULT, /* based on data in mv_ddr_topology_map structure */
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MV_DDR_CFG_SPD, /* based on data in spd */
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MV_DDR_CFG_USER, /* based on data from user */
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MV_DDR_CFG_STATIC, /* based on data from user in register-value format */
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MV_DDR_CFG_LAST
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};
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enum mv_ddr_temperature {
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MV_DDR_TEMP_LOW,
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MV_DDR_TEMP_NORMAL,
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MV_DDR_TEMP_HIGH
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};
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enum mv_ddr_timing {
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MV_DDR_TIM_DEFAULT,
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MV_DDR_TIM_1T,
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MV_DDR_TIM_2T
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};
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enum mv_ddr_timing_data {
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MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
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MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */
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MV_DDR_TRFC1_MIN, /* min refresh recovery delay time (t rfc1 min) */
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MV_DDR_TWR_MIN, /* min write recovery time (t wr min) */
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MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */
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MV_DDR_TRP_MIN, /* min row precharge delay time (t rp min) */
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MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */
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MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
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MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
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MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
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MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */
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MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */
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MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
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MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */
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MV_DDR_TDATA_LAST
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};
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enum mv_ddr_electrical_data {
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MV_DDR_CK_DLY,
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MV_DDR_PHY_REG3,
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MV_DDR_ZPRI_DATA,
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MV_DDR_ZNRI_DATA,
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MV_DDR_ZPRI_CTRL,
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MV_DDR_ZNRI_CTRL,
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MV_DDR_ZPODT_DATA,
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MV_DDR_ZNODT_DATA,
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MV_DDR_ZPODT_CTRL,
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MV_DDR_ZNODT_CTRL,
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MV_DDR_DIC,
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MV_DDR_ODT_CFG,
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MV_DDR_RTT_NOM,
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MV_DDR_RTT_WR,
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MV_DDR_RTT_PARK,
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MV_DDR_EDATA_LAST
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};
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/* memory electrical configuration values */
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enum mv_ddr_rtt_nom_park_evalue {
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* 60-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV6, /* 40-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_NOM_PARK_RZQ_LAST
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};
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enum mv_ddr_rtt_wr_evalue {
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MV_DDR_RTT_WR_DYN_ODT_OFF,
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MV_DDR_RTT_WR_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_WR_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_WR_HIZ,
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MV_DDR_RTT_WR_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
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MV_DDR_RTT_WR_RZQ_LAST
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};
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enum mv_ddr_dic_evalue {
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MV_DDR_DIC_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
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MV_DDR_DIC_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */
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MV_DDR_DIC_RZQ_LAST
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};
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/* phy electrical configuration values */
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enum mv_ddr_ohm_evalue {
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MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
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MV_DDR_OHM_30 = 30,
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MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
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MV_DDR_OHM_48 = 48,
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MV_DDR_OHM_60 = 60,
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MV_DDR_OHM_80 = 80,
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MV_DDR_OHM_120 = 120,
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MV_DDR_OHM_240 = 240,
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MV_DDR_OHM_LAST
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};
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/* mac electrical configuration values */
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enum mv_ddr_odt_cfg_evalue {
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MV_DDR_ODT_CFG_NORMAL,
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MV_DDR_ODT_CFG_ALWAYS_ON,
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MV_DDR_ODT_CFG_LAST
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};
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enum mv_ddr_dev_width { /* sdram device width */
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MV_DDR_DEV_WIDTH_4BIT,
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MV_DDR_DEV_WIDTH_8BIT,
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MV_DDR_DEV_WIDTH_16BIT,
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MV_DDR_DEV_WIDTH_32BIT,
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MV_DDR_DEV_WIDTH_LAST
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};
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enum mv_ddr_die_capacity { /* total sdram capacity per die, megabits */
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MV_DDR_DIE_CAP_256MBIT,
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MV_DDR_DIE_CAP_512MBIT = 0,
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MV_DDR_DIE_CAP_1GBIT,
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MV_DDR_DIE_CAP_2GBIT,
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MV_DDR_DIE_CAP_4GBIT,
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MV_DDR_DIE_CAP_8GBIT,
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MV_DDR_DIE_CAP_16GBIT,
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MV_DDR_DIE_CAP_32GBIT,
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MV_DDR_DIE_CAP_12GBIT,
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MV_DDR_DIE_CAP_24GBIT,
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MV_DDR_DIE_CAP_LAST
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};
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enum mv_ddr_pkg_rank { /* number of package ranks per dimm */
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MV_DDR_PKG_RANK_1,
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MV_DDR_PKG_RANK_2,
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MV_DDR_PKG_RANK_3,
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MV_DDR_PKG_RANK_4,
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MV_DDR_PKG_RANK_5,
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MV_DDR_PKG_RANK_6,
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MV_DDR_PKG_RANK_7,
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MV_DDR_PKG_RANK_8,
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MV_DDR_PKG_RANK_LAST
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};
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enum mv_ddr_pri_bus_width { /* number of primary bus width bits */
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MV_DDR_PRI_BUS_WIDTH_8,
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MV_DDR_PRI_BUS_WIDTH_16,
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MV_DDR_PRI_BUS_WIDTH_32,
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MV_DDR_PRI_BUS_WIDTH_64,
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MV_DDR_PRI_BUS_WIDTH_LAST
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};
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enum mv_ddr_bus_width_ext { /* number of extension bus width bits */
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MV_DDR_BUS_WIDTH_EXT_0,
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MV_DDR_BUS_WIDTH_EXT_8,
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MV_DDR_BUS_WIDTH_EXT_LAST
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};
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enum mv_ddr_die_count {
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MV_DDR_DIE_CNT_1,
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MV_DDR_DIE_CNT_2,
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MV_DDR_DIE_CNT_3,
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MV_DDR_DIE_CNT_4,
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MV_DDR_DIE_CNT_5,
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MV_DDR_DIE_CNT_6,
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MV_DDR_DIE_CNT_7,
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MV_DDR_DIE_CNT_8,
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MV_DDR_DIE_CNT_LAST
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};
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#define IS_ACTIVE(mask, id) \
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((mask) & (1 << (id)))
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#define VALIDATE_ACTIVE(mask, id) \
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{ \
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if (IS_ACTIVE(mask, id) == 0) \
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continue; \
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}
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#define IS_IF_ACTIVE(if_mask, if_id) \
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((if_mask) & (1 << (if_id)))
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#define VALIDATE_IF_ACTIVE(mask, id) \
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{ \
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if (IS_IF_ACTIVE(mask, id) == 0) \
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continue; \
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}
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#define IS_BUS_ACTIVE(if_mask , if_id) \
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(((if_mask) >> (if_id)) & 1)
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#define VALIDATE_BUS_ACTIVE(mask, id) \
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{ \
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if (IS_BUS_ACTIVE(mask, id) == 0) \
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continue; \
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}
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#define DDR3_IS_ECC_PUP3_MODE(if_mask) \
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(((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
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#define DDR3_IS_ECC_PUP4_MODE(if_mask) \
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(((if_mask) == BUS_MASK_32BIT_ECC || \
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(if_mask) == BUS_MASK_16BIT_ECC) ? 1 : 0)
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#define DDR3_IS_16BIT_DRAM_MODE(mask) \
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(((mask) == BUS_MASK_16BIT || \
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(mask) == BUS_MASK_16BIT_ECC || \
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(mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
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#define DDR3_IS_ECC_PUP8_MODE(if_mask) \
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(((if_mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || \
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(if_mask) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
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#define MV_DDR_IS_64BIT_DRAM_MODE(mask) \
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((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \
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(((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
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#define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) \
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(((sphys) == 9) && \
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(((mask) == BUS_MASK_32BIT) || \
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((mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0)
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#define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, sphys) \
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(MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) || \
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DDR3_IS_16BIT_DRAM_MODE(mask))
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
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unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk);
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unsigned int mv_ddr_cwl_calc(unsigned int tclk);
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int mv_ddr_topology_map_update(void);
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unsigned short mv_ddr_bus_bit_mask_get(void);
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unsigned int mv_ddr_if_bus_width_get(void);
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unsigned int mv_ddr_cs_num_get(void);
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int mv_ddr_is_ecc_ena(void);
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int mv_ddr_ck_delay_get(void);
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unsigned long long mv_ddr_mem_sz_per_cs_get(void);
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unsigned long long mv_ddr_mem_sz_get(void);
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unsigned int mv_ddr_rtt_nom_get(void);
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unsigned int mv_ddr_rtt_park_get(void);
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unsigned int mv_ddr_rtt_wr_get(void);
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unsigned int mv_ddr_dic_get(void);
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#endif /* _MV_DDR_TOPOLOGY_H */
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