398 lines
9.9 KiB
C
398 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <common.h>
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#include <command.h>
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#include <div64.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pcc.h>
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#include <asm/arch/cgc.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6)
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#define PLL_USB_PWR_MASK (0x01 << 12)
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#define PLL_USB_ENABLE_MASK (0x01 << 13)
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#define PLL_USB_BYPASS_MASK (0x01 << 16)
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#define PLL_USB_REG_ENABLE_MASK (0x01 << 21)
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#define PLL_USB_DIV_SEL_MASK (0x07 << 22)
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#define PLL_USB_LOCK_MASK (0x01 << 31)
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#define PCC5_LPDDR4_ADDR 0x2da70108
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static void lpuart_set_clk(u32 index, enum cgc1_clk clk)
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{
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const u32 lpuart_pcc_slots[] = {
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LPUART4_PCC3_SLOT,
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LPUART5_PCC3_SLOT,
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LPUART6_PCC4_SLOT,
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LPUART7_PCC4_SLOT,
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};
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const u32 lpuart_pcc[] = {
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3, 3, 4, 4,
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};
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if (index > 3)
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return;
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pcc_clock_enable(lpuart_pcc[index], lpuart_pcc_slots[index], false);
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pcc_clock_sel(lpuart_pcc[index], lpuart_pcc_slots[index], clk);
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pcc_clock_enable(lpuart_pcc[index], lpuart_pcc_slots[index], true);
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pcc_reset_peripheral(lpuart_pcc[index], lpuart_pcc_slots[index], false);
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}
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static void init_clk_lpuart(void)
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{
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u32 index = 0, i;
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const u32 lpuart_array[] = {
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LPUART4_RBASE,
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LPUART5_RBASE,
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LPUART6_RBASE,
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LPUART7_RBASE,
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};
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for (i = 0; i < 4; i++) {
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if (lpuart_array[i] == LPUART_BASE) {
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index = i;
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break;
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}
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}
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lpuart_set_clk(index, SOSC_DIV2);
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}
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void init_clk_fspi(int index)
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{
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pcc_clock_enable(4, FLEXSPI2_PCC4_SLOT, false);
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pcc_clock_sel(4, FLEXSPI2_PCC4_SLOT, PLL3_PFD2_DIV1);
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pcc_clock_div_config(4, FLEXSPI2_PCC4_SLOT, false, 8);
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pcc_clock_enable(4, FLEXSPI2_PCC4_SLOT, true);
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pcc_reset_peripheral(4, FLEXSPI2_PCC4_SLOT, false);
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}
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void setclkout_ddr(void)
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{
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writel(0x12800000, 0x2DA60020);
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writel(0xa00, 0x298C0000); /* PTD0 */
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}
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void ddrphy_pll_lock(void)
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{
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writel(0x00011542, 0x2E065964);
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writel(0x00011542, 0x2E06586C);
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writel(0x00000B01, 0x2E062000);
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writel(0x00000B01, 0x2E060000);
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}
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void init_clk_ddr(void)
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{
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/* enable pll4 and ddrclk*/
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cgc2_pll4_init();
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cgc2_ddrclk_config(1, 1);
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/* enable ddr pcc */
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writel(0xd0000000, PCC5_LPDDR4_ADDR);
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/* for debug */
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/* setclkout_ddr(); */
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}
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int set_ddr_clk(u32 phy_freq_mhz)
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{
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debug("%s %u\n", __func__, phy_freq_mhz);
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if (phy_freq_mhz == 48) {
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writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */
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cgc2_ddrclk_config(2, 0); /* 24Mhz DDR clock */
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writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */
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} else if (phy_freq_mhz == 384) {
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writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */
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cgc2_ddrclk_config(0, 0); /* 192Mhz DDR clock */
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writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */
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} else if (phy_freq_mhz == 528) {
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writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */
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cgc2_ddrclk_config(4, 1); /* 264Mhz DDR clock */
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writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */
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} else if (phy_freq_mhz == 264) {
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writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */
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cgc2_ddrclk_config(4, 3); /* 132Mhz DDR clock */
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writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */
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} else if (phy_freq_mhz == 192) {
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writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */
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cgc2_ddrclk_config(0, 1); /* 96Mhz DDR clock */
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writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */
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} else if (phy_freq_mhz == 96) {
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writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */
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cgc2_ddrclk_config(0, 3); /* 48Mhz DDR clock */
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writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */
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} else {
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printf("ddr phy clk %uMhz is not supported\n", phy_freq_mhz);
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return -EINVAL;
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}
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return 0;
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}
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void clock_init(void)
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{
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cgc1_soscdiv_init();
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cgc1_init_core_clk();
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init_clk_lpuart();
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pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
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pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
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pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
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pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
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pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
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pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
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pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
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pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
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pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
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pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
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pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
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pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
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/* Enable upower mu1 clk */
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pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
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/*
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* Enable clock division
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* TODO: may not needed after ROM ready.
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*/
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}
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#if IS_ENABLED(CONFIG_SYS_I2C_IMX_LPI2C)
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int enable_i2c_clk(unsigned char enable, u32 i2c_num)
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{
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/* Set parent to FIRC DIV2 clock */
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const u32 lpi2c_pcc_clks[] = {
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LPI2C4_PCC3_SLOT << 8 | 3,
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LPI2C5_PCC3_SLOT << 8 | 3,
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LPI2C6_PCC4_SLOT << 8 | 4,
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LPI2C7_PCC4_SLOT << 8 | 4,
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};
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if (i2c_num < 4 || i2c_num > 7)
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return -EINVAL;
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if (enable) {
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pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4] & 0xff,
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lpi2c_pcc_clks[i2c_num - 4] >> 8, false);
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pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4] & 0xff,
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lpi2c_pcc_clks[i2c_num - 4] >> 8, SOSC_DIV2);
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pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4] & 0xff,
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lpi2c_pcc_clks[i2c_num - 4] >> 8, true);
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pcc_reset_peripheral(lpi2c_pcc_clks[i2c_num - 4] & 0xff,
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lpi2c_pcc_clks[i2c_num - 4] >> 8, false);
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} else {
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pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4] & 0xff,
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lpi2c_pcc_clks[i2c_num - 4] >> 8, false);
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}
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return 0;
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}
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u32 imx_get_i2cclk(u32 i2c_num)
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{
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const u32 lpi2c_pcc_clks[] = {
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LPI2C4_PCC3_SLOT << 8 | 3,
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LPI2C5_PCC3_SLOT << 8 | 3,
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LPI2C6_PCC4_SLOT << 8 | 4,
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LPI2C7_PCC4_SLOT << 8 | 4,
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};
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if (i2c_num < 4 || i2c_num > 7)
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return 0;
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return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4] & 0xff,
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lpi2c_pcc_clks[i2c_num - 4] >> 8);
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}
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#endif
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void enable_usboh3_clk(unsigned char enable)
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{
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if (enable) {
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pcc_clock_enable(4, USB0_PCC4_SLOT, true);
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pcc_clock_enable(4, USBPHY_PCC4_SLOT, true);
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pcc_reset_peripheral(4, USB0_PCC4_SLOT, false);
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pcc_reset_peripheral(4, USBPHY_PCC4_SLOT, false);
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#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
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if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
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pcc_clock_enable(4, USB1_PCC4_SLOT, true);
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pcc_clock_enable(4, USB1PHY_PCC4_SLOT, true);
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pcc_reset_peripheral(4, USB1_PCC4_SLOT, false);
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pcc_reset_peripheral(4, USB1PHY_PCC4_SLOT, false);
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}
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#endif
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pcc_clock_enable(4, USB_XBAR_PCC4_SLOT, true);
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} else {
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pcc_clock_enable(4, USB0_PCC4_SLOT, false);
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pcc_clock_enable(4, USB1_PCC4_SLOT, false);
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pcc_clock_enable(4, USBPHY_PCC4_SLOT, false);
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pcc_clock_enable(4, USB1PHY_PCC4_SLOT, false);
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pcc_clock_enable(4, USB_XBAR_PCC4_SLOT, false);
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}
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}
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int enable_usb_pll(ulong usb_phy_base)
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{
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u32 sosc_rate;
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s32 timeout = 1000000;
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struct usbphy_regs *usbphy =
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(struct usbphy_regs *)usb_phy_base;
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sosc_rate = cgc1_sosc_div(SOSC);
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if (!sosc_rate)
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return -EPERM;
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if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
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writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
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switch (sosc_rate) {
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case 24000000:
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writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
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break;
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case 30000000:
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writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
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break;
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case 19200000:
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writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
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break;
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default:
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writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
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break;
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}
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/* Enable the regulator first */
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writel(PLL_USB_REG_ENABLE_MASK,
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&usbphy->usb1_pll_480_ctrl_set);
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/* Wait at least 15us */
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udelay(15);
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/* Enable the power */
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writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
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/* Wait lock */
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while (timeout--) {
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if (readl(&usbphy->usb1_pll_480_ctrl) &
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PLL_USB_LOCK_MASK)
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break;
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}
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if (timeout <= 0) {
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/* If timeout, we power down the pll */
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writel(PLL_USB_PWR_MASK,
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&usbphy->usb1_pll_480_ctrl_clr);
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return -ETIME;
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}
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}
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/* Clear the bypass */
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writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
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/* Enable the PLL clock out to USB */
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writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
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&usbphy->usb1_pll_480_ctrl_set);
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return 0;
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}
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u32 mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ESDHC_CLK:
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return pcc_clock_get_rate(4, SDHC0_PCC4_SLOT);
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case MXC_ESDHC2_CLK:
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return pcc_clock_get_rate(4, SDHC1_PCC4_SLOT);
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case MXC_ESDHC3_CLK:
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return pcc_clock_get_rate(4, SDHC2_PCC4_SLOT);
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case MXC_ARM_CLK:
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return cgc1_clk_get_rate(PLL2);
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default:
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return 0;
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}
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}
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u32 get_lpuart_clk(void)
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{
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int index = 0;
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const u32 lpuart_array[] = {
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LPUART4_RBASE,
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LPUART5_RBASE,
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LPUART6_RBASE,
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LPUART7_RBASE,
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};
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const u32 lpuart_pcc_slots[] = {
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LPUART4_PCC3_SLOT,
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LPUART5_PCC3_SLOT,
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LPUART6_PCC4_SLOT,
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LPUART7_PCC4_SLOT,
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};
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const u32 lpuart_pcc[] = {
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3, 3, 4, 4,
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};
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for (index = 0; index < 4; index++) {
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if (lpuart_array[index] == LPUART_BASE)
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break;
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}
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if (index > 3)
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return 0;
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return pcc_clock_get_rate(lpuart_pcc[index], lpuart_pcc_slots[index]);
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}
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#ifndef CONFIG_SPL_BUILD
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/*
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* Dump some core clockes.
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*/
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int do_mx8ulp_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
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{
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printf("SDHC0 %8d MHz\n", pcc_clock_get_rate(4, SDHC0_PCC4_SLOT) / 1000000);
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printf("SDHC1 %8d MHz\n", pcc_clock_get_rate(4, SDHC1_PCC4_SLOT) / 1000000);
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printf("SDHC2 %8d MHz\n", pcc_clock_get_rate(4, SDHC2_PCC4_SLOT) / 1000000);
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printf("SOSC %8d MHz\n", cgc1_clk_get_rate(SOSC) / 1000000);
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printf("FRO %8d MHz\n", cgc1_clk_get_rate(FRO) / 1000000);
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printf("PLL2 %8d MHz\n", cgc1_clk_get_rate(PLL2) / 1000000);
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printf("PLL3 %8d MHz\n", cgc1_clk_get_rate(PLL3) / 1000000);
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printf("PLL3_VCODIV %8d MHz\n", cgc1_clk_get_rate(PLL3_VCODIV) / 1000000);
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printf("PLL3_PFD0 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD0) / 1000000);
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printf("PLL3_PFD1 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD1) / 1000000);
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printf("PLL3_PFD2 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD2) / 1000000);
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printf("PLL3_PFD3 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD3) / 1000000);
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_mx8ulp_showclocks,
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"display clocks",
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""
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);
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#endif
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