412 lines
9.2 KiB
C
412 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mu_hal.h>
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#include <asm/arch/s400_api.h>
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#include <asm/arch/rdc.h>
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#include <div64.h>
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#define XRDC_ADDR 0x292f0000
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#define MRC_OFFSET 0x2000
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#define MRC_STEP 0x200
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#define SP(X) ((X) << 9)
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#define SU(X) ((X) << 6)
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#define NP(X) ((X) << 3)
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#define NU(X) ((X) << 0)
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#define RWX 7
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#define RW 6
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#define R 4
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#define X 1
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#define D7SEL_CODE (SP(RW) | SU(RW) | NP(RWX) | NU(RWX))
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#define D6SEL_CODE (SP(RW) | SU(RW) | NP(RWX))
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#define D5SEL_CODE (SP(RW) | SU(RWX))
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#define D4SEL_CODE SP(RWX)
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#define D3SEL_CODE (SP(X) | SU(X) | NP(X) | NU(X))
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#define D0SEL_CODE 0
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#define D7SEL_DAT (SP(RW) | SU(RW) | NP(RW) | NU(RW))
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#define D6SEL_DAT (SP(RW) | SU(RW) | NP(RW))
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#define D5SEL_DAT (SP(RW) | SU(RW) | NP(R) | NU(R))
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#define D4SEL_DAT (SP(RW) | SU(RW))
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#define D3SEL_DAT SP(RW)
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struct mbc_mem_dom {
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u32 mem_glbcfg[4];
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u32 nse_blk_index;
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u32 nse_blk_set;
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u32 nse_blk_clr;
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u32 nsr_blk_clr_all;
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u32 memn_glbac[8];
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/* The upper only existed in the beginning of each MBC */
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u32 mem0_blk_cfg_w[64];
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u32 mem0_blk_nse_w[16];
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u32 mem1_blk_cfg_w[8];
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u32 mem1_blk_nse_w[2];
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u32 mem2_blk_cfg_w[8];
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u32 mem2_blk_nse_w[2];
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u32 mem3_blk_cfg_w[8];
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u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
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u32 reserved[2];
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};
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struct mrc_rgn_dom {
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u32 mrc_glbcfg[4];
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u32 nse_rgn_indirect;
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u32 nse_rgn_set;
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u32 nse_rgn_clr;
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u32 nse_rgn_clr_all;
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u32 memn_glbac[8];
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/* The upper only existed in the beginning of each MRC */
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u32 rgn_desc_words[8][2]; /* 8 regions, 2 words per region */
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u32 reserved[16];
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u32 rgn_nse;
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u32 reserved2[15];
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};
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struct trdc {
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u8 res0[0x1000];
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struct mbc_mem_dom mem_dom[4][8];
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struct mrc_rgn_dom mrc_dom[2][8];
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};
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union dxsel_perm {
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struct {
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u8 dx;
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u8 perm;
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};
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u32 dom_perm;
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};
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int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel)
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{
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ulong w2_addr;
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u32 val = 0;
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w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8;
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val = (readl(w2_addr) & (~(7 << (3 * dom)))) | (dxsel << (3 * dom));
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writel(val, w2_addr);
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return 0;
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}
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int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size)
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{
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ulong w0_addr, w1_addr;
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w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
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w1_addr = w0_addr + 4;
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if ((size % 32) != 0)
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return -EINVAL;
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writel(w0 & ~0x1f, w0_addr);
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writel(w0 + size - 1, w1_addr);
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return 0;
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}
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int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4)
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{
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ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC;
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ulong w4_addr = w3_addr + 4;
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writel(w3, w3_addr);
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writel(w4, w4_addr);
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return 0;
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}
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int xrdc_config_pdac_openacc(u32 bridge, u32 index)
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{
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ulong w0_addr;
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u32 val;
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switch (bridge) {
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case 3:
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w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
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break;
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case 4:
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w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
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break;
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case 5:
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w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
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break;
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default:
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return -EINVAL;
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}
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writel(0xffffff, w0_addr);
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val = readl(w0_addr + 4);
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writel(val | BIT(31), w0_addr + 4);
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return 0;
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}
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int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
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{
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ulong w0_addr;
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u32 val;
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switch (bridge) {
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case 3:
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w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
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break;
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case 4:
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w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
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break;
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case 5:
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w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
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break;
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default:
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return -EINVAL;
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}
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val = readl(w0_addr);
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writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);
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val = readl(w0_addr + 4);
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writel(val | BIT(31), w0_addr + 4);
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return 0;
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}
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int release_rdc(enum rdc_type type)
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{
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ulong s_mu_base = 0x27020000UL;
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struct imx8ulp_s400_msg msg;
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int ret;
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u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
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msg.version = AHAB_VERSION;
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msg.tag = AHAB_CMD_TAG;
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msg.size = 2;
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msg.command = AHAB_RELEASE_RDC_REQ_CID;
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msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
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mu_hal_init(s_mu_base);
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mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
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mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
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ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
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if (!ret) {
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ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
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if (!ret) {
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if ((msg.data[0] & 0xff) == 0xd6)
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return 0;
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}
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return -EIO;
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}
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return ret;
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}
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void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
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{
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ulong xrdc_base = 0x292f0000, off;
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u32 mrgd[5];
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u8 mrcfg, j, region_num;
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u8 dsel;
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mrcfg = readb(xrdc_base + 0x140 + mrc_index);
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region_num = mrcfg & 0x1f;
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for (j = 0; j < region_num; j++) {
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off = 0x2000 + mrc_index * 0x200 + j * 0x20;
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mrgd[0] = readl(xrdc_base + off);
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mrgd[1] = readl(xrdc_base + off + 4);
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mrgd[2] = readl(xrdc_base + off + 8);
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mrgd[3] = readl(xrdc_base + off + 0xc);
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mrgd[4] = readl(xrdc_base + off + 0x10);
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debug("MRC [%u][%u]\n", mrc_index, j);
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debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
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mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]);
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/* hit */
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if (addr >= mrgd[0] && addr <= mrgd[1]) {
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/* find domain 7 DSEL */
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dsel = (mrgd[2] >> 21) & 0x7;
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if (dsel == 1) {
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mrgd[4] &= ~0xFFF;
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mrgd[4] |= (access & 0xFFF);
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} else if (dsel == 2) {
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mrgd[4] &= ~0xFFF0000;
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mrgd[4] |= ((access & 0xFFF) << 16);
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}
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/* not handle other cases, since S400 only set ACCESS1 and 2 */
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writel(mrgd[4], xrdc_base + off + 0x10);
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return;
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}
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}
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}
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void xrdc_init_mda(void)
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{
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ulong xrdc_base = XRDC_ADDR, off;
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u32 i = 0;
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/* Set MDA3-5 for PXP, ENET, CAAM to DID 1*/
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for (i = 3; i <= 5; i++) {
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off = 0x800 + i * 0x20;
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writel(0x200000A1, xrdc_base + off);
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writel(0xA00000A1, xrdc_base + off);
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}
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/* Set MDA10 -15 to DID 3 for video */
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for (i = 10; i <= 15; i++) {
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off = 0x800 + i * 0x20;
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writel(0x200000A3, xrdc_base + off);
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writel(0xA00000A3, xrdc_base + off);
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}
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}
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void xrdc_init_mrc(void)
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{
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/* The MRC8 is for SRAM1 */
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xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
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/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
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xrdc_config_mrc_dx_perm(8, 0, 0, 1);
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xrdc_config_mrc_dx_perm(8, 0, 1, 1);
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xrdc_config_mrc_dx_perm(8, 0, 2, 1);
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xrdc_config_mrc_dx_perm(8, 0, 3, 1);
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xrdc_config_mrc_dx_perm(8, 0, 4, 1);
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xrdc_config_mrc_dx_perm(8, 0, 5, 1);
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xrdc_config_mrc_dx_perm(8, 0, 6, 1);
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xrdc_config_mrc_dx_perm(8, 0, 7, 1);
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xrdc_config_mrc_w3_w4(8, 0, 0x0, 0x80000FFF);
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/* The MRC6 is for video modules to ddr */
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xrdc_config_mrc_w0_w1(6, 0, 0x80000000, 0x80000000);
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xrdc_config_mrc_dx_perm(6, 0, 3, 1); /* allow for domain 3 video */
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xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
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}
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int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access)
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{
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struct trdc *trdc_base = (struct trdc *)0x28031000U;
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struct mbc_mem_dom *mbc_dom;
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u32 *cfg_w, *nse_w;
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u32 index, offset, val;
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mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x];
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switch (mem_x) {
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case 0:
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cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
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break;
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case 1:
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cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
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break;
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case 2:
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cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
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break;
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case 3:
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cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
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break;
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default:
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return -EINVAL;
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};
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index = blk_x % 8;
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offset = index * 4;
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val = readl((void __iomem *)cfg_w);
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val &= ~(0xFU << offset);
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/* MBC0-3
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* Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
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* So select MBC0_MEMN_GLBAC0
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*/
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if (sec_access) {
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val |= (0x0 << offset);
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writel(val, (void __iomem *)cfg_w);
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} else {
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val |= (0x8 << offset); /* nse bit set */
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writel(val, (void __iomem *)cfg_w);
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}
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return 0;
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}
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int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access)
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{
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struct trdc *trdc_base = (struct trdc *)0x28031000U;
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struct mrc_rgn_dom *mrc_dom;
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u32 *desc_w;
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u32 start, end;
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u32 i, free = 8;
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bool vld, hit = false;
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mrc_dom = &trdc_base->mrc_dom[mrc_x][dom_x];
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for (i = 0; i < 8; i++) {
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desc_w = &mrc_dom->rgn_desc_words[i][0];
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start = readl((void __iomem *)desc_w) & 0xfff;
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end = readl((void __iomem *)(desc_w + 1));
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vld = end & 0x1;
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end = end & 0xfff;
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if (start == 0 && end == 0 && !vld && free >= 8)
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free = i;
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/* Check all the region descriptors, even overlap */
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if (addr_start >= end || addr_end <= start || !vld)
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continue;
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/* MRC0,1
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* Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
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* So select MRCx_MEMN_GLBAC0
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*/
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if (sec_access) {
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writel(start, (void __iomem *)desc_w);
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writel(end | 0x1, (void __iomem *)(desc_w + 1));
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} else {
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writel(start, (void __iomem *)desc_w);
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writel((end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
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}
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if (addr_start >= start && addr_end <= end)
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hit = true;
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}
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if (!hit) {
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if (free >= 8)
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return -EFAULT;
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desc_w = &mrc_dom->rgn_desc_words[free][0];
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addr_start &= ~0xfff;
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addr_end &= ~0xfff;
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if (sec_access) {
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writel(addr_start, (void __iomem *)desc_w);
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writel(addr_end | 0x1, (void __iomem *)(desc_w + 1));
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} else {
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writel(addr_start, (void __iomem *)desc_w);
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writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
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}
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}
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return 0;
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}
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