200 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			200 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * Copyright (C) 2016 Freescale Semiconductor, Inc.
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|  */
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| 
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| #include <common.h>
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| #include <log.h>
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| #include <asm/io.h>
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| #include <asm/mach-imx/sys_proto.h>
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| #include <command.h>
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| #include <elf.h>
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| #include <imx_sip.h>
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| #include <linux/arm-smccc.h>
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| #include <linux/compiler.h>
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| #include <cpu_func.h>
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| 
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| #ifndef CONFIG_IMX8M
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| const __weak struct rproc_att hostmap[] = { };
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| 
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| static const struct rproc_att *get_host_mapping(unsigned long auxcore)
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| {
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| 	const struct rproc_att *mmap = hostmap;
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| 
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| 	while (mmap && mmap->size) {
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| 		if (mmap->da <= auxcore &&
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| 		    mmap->da + mmap->size > auxcore)
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| 			return mmap;
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| 		mmap++;
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| 	}
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| 
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| 	return NULL;
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| }
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| 
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| /*
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|  * A very simple elf loader for the auxilary core, assumes the image
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|  * is valid, returns the entry point address.
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|  * Translates load addresses in the elf file to the U-Boot address space.
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|  */
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| static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
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| {
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| 	Elf32_Ehdr *ehdr; /* ELF header structure pointer */
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| 	Elf32_Phdr *phdr; /* Program header structure pointer */
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| 	int i;
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| 
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| 	ehdr = (Elf32_Ehdr *)addr;
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| 	phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
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| 
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| 	/* Load each program header */
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| 	for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) {
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| 		const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr);
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| 		void *dst, *src;
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| 
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| 		if (phdr->p_type != PT_LOAD)
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| 			continue;
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| 
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| 		if (!mmap) {
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| 			printf("Invalid aux core address: %08x",
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| 			       phdr->p_paddr);
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| 			return 0;
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| 		}
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| 
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| 		dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa;
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| 		src = (void *)addr + phdr->p_offset;
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| 
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| 		debug("Loading phdr %i to 0x%p (%i bytes)\n",
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| 		      i, dst, phdr->p_filesz);
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| 
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| 		if (phdr->p_filesz)
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| 			memcpy(dst, src, phdr->p_filesz);
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| 		if (phdr->p_filesz != phdr->p_memsz)
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| 			memset(dst + phdr->p_filesz, 0x00,
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| 			       phdr->p_memsz - phdr->p_filesz);
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| 		flush_cache((unsigned long)dst &
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| 			    ~(CONFIG_SYS_CACHELINE_SIZE - 1),
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| 			    ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE));
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| 	}
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| 
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| 	return ehdr->e_entry;
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| }
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| #endif
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| 
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| int arch_auxiliary_core_up(u32 core_id, ulong addr)
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| {
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| 	ulong stack, pc;
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| 
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| 	if (!addr)
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| 		return -EINVAL;
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| 
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| #ifdef CONFIG_IMX8M
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| 	stack = *(u32 *)addr;
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| 	pc = *(u32 *)(addr + 4);
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| #else
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| 	/*
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| 	 * handling ELF64 binaries
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| 	 * isn't supported yet.
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| 	 */
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| 	if (valid_elf_image(addr)) {
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| 		stack = 0x0;
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| 		pc = load_elf_image_m_core_phdr(addr);
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| 		if (!pc)
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| 			return CMD_RET_FAILURE;
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| 
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| 	} else {
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| 		/*
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| 		 * Assume binary file with vector table at the beginning.
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| 		 * Cortex-M4 vector tables start with the stack pointer (SP)
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| 		 * and reset vector (initial PC).
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| 		 */
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| 		stack = *(u32 *)addr;
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| 		pc = *(u32 *)(addr + 4);
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| 	}
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| #endif
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| 	printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
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| 	       stack, pc);
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| 
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| 	/* Set the stack and pc to M4 bootROM */
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| 	writel(stack, M4_BOOTROM_BASE_ADDR);
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| 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
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| 
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| 	flush_dcache_all();
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| 
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| 	/* Enable M4 */
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| #ifdef CONFIG_IMX8M
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| 	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
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| 		      0, 0, 0, 0, NULL);
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| #else
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| 	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
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| 			SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
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| #endif
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| 
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| 	return 0;
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| }
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| 
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| int arch_auxiliary_core_check_up(u32 core_id)
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| {
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| #ifdef CONFIG_IMX8M
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| 	struct arm_smccc_res res;
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| 
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| 	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
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| 		      0, 0, 0, 0, &res);
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| 
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| 	return res.a0;
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| #else
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| 	unsigned int val;
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| 
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| 	val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
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| 
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| 	if (val & SRC_M4C_NON_SCLR_RST_MASK)
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| 		return 0;  /* assert in reset */
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| 
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| 	return 1;
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| #endif
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| }
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| 
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| /*
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|  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
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|  * the reset vector at the head for the image, with SP and PC
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|  * as the first two words.
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|  *
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|  * Per the cortex-M reference manual, the reset vector of M4 needs
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|  * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
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|  * of that vector.  So to boot M4, the A core must build the M4's reset
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|  * vector with getting the PC and SP from image and filling them to
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|  * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
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|  * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
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|  * accessing the M4 TCMUL.
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|  */
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| static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
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| 		      char *const argv[])
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| {
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| 	ulong addr;
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| 	int ret, up;
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| 
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| 	if (argc < 2)
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| 		return CMD_RET_USAGE;
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| 
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| 	up = arch_auxiliary_core_check_up(0);
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| 	if (up) {
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| 		printf("## Auxiliary core is already up\n");
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| 		return CMD_RET_SUCCESS;
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| 	}
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| 
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| 	addr = hextoul(argv[1], NULL);
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| 
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| 	if (!addr)
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| 		return CMD_RET_FAILURE;
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| 
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| 	ret = arch_auxiliary_core_up(0, addr);
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| 	if (ret)
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| 		return CMD_RET_FAILURE;
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| 
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| 	return CMD_RET_SUCCESS;
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| }
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| 
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| U_BOOT_CMD(
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| 	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
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| 	"Start auxiliary core",
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| 	""
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| );
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