117 lines
2.5 KiB
C
117 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <command.h>
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#include <init.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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void cm_wait_for_lock(u32 mask)
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{
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u32 inter_val;
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u32 retry = 0;
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do {
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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inter_val = readl(socfpga_get_clkmgr_addr() +
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CLKMGR_INTER) & mask;
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#else
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inter_val = readl(socfpga_get_clkmgr_addr() +
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CLKMGR_STAT) & mask;
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#endif
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/* Wait for stable lock */
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if (inter_val == mask)
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retry++;
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else
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retry = 0;
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if (retry >= 10)
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break;
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} while (1);
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}
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/* function to poll in the fsm busy bit */
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int cm_wait_for_fsm(void)
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{
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return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
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CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
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false);
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}
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int set_cpu_clk_info(void)
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{
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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/* Calculate the clock frequencies required for drivers */
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cm_get_l4_sp_clk_hz();
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cm_get_mmc_controller_clk_hz();
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#endif
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gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
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gd->bd->bi_dsp_freq = 0;
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
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#else
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gd->bd->bi_ddr_freq = 0;
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#endif
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return 0;
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}
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
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int cm_set_qspi_controller_clk_hz(u32 clk_hz)
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{
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u32 reg;
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u32 clk_khz;
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/*
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* Store QSPI ref clock and set into sysmgr boot register.
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* Only clock freq in kHz degree is accepted due to limited bits[27:0]
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* is reserved for storing the QSPI clock freq into boot scratch cold0
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* register.
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*/
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if (clk_hz < 1000)
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return -EINVAL;
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clk_khz = clk_hz / 1000;
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printf("QSPI: Reference clock at %d kHz\n", clk_khz);
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reg = (readl(socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
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~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
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writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
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return 0;
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}
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unsigned int cm_get_qspi_controller_clk_hz(void)
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{
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return (readl(socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
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SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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cm_print_clock_quick_summary();
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
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"display clocks",
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""
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);
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#endif
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