77 lines
1.5 KiB
ArmAsm
77 lines
1.5 KiB
ArmAsm
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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ENTRY(lowlevel_init)
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mov x29, lr /* Save LR */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
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wait_for_atf:
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ldr x4, =CPU_RELEASE_ADDR
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ldr x5, [x4]
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cbz x5, slave_wait_atf
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br x5
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slave_wait_atf:
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branch_if_slave x0, wait_for_atf
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#else
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branch_if_slave x0, 1f
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#endif
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ldr x0, =GICD_BASE
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bl gic_init_secure
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1:
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#if defined(CONFIG_GICV3)
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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#endif
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, 2f
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent slaves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#ifdef CONFIG_GICV2
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ldr x0, =GICC_BASE
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#endif
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bl gic_wait_for_interrupt
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#endif
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/*
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* All slaves will enter EL2 and optionally EL1.
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*/
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adr x4, lowlevel_in_el2
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el2
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lowlevel_in_el2:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, lowlevel_in_el1
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el1
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lowlevel_in_el1:
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#endif
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2:
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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