396 lines
9.7 KiB
C
396 lines
9.7 KiB
C
/*
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* Dave Ethernet Controller driver
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*
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* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <log.h>
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#include <linux/delay.h>
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#ifndef CONFIG_DNET_AUTONEG_TIMEOUT
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#define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
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#endif
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#include <net.h>
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#include <malloc.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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#include "dnet.h"
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struct dnet_device {
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struct dnet_registers *regs;
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const struct device *dev;
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struct eth_device netdev;
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unsigned short phy_addr;
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};
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/* get struct dnet_device from given struct netdev */
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#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
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/* function for reading internal MAC register */
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u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg)
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{
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u16 data_read;
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/* issue a read */
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writel(reg, &dnet->regs->MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before reading the data */
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udelay(1);
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/* read data read from the MAC register */
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data_read = readl(&dnet->regs->MACREG_DATA);
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/* all done */
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return data_read;
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}
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/* function for writing internal MAC register */
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void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val)
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{
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/* load data to write */
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writel(val, &dnet->regs->MACREG_DATA);
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/* issue a write */
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writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before exiting */
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udelay(1);
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}
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static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value)
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{
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u16 tmp;
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debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",
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dnet->phy_addr, reg, value);
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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/* prepare for a write operation */
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tmp = (1 << 13);
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/* only 5 bits allowed for register offset */
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reg &= 0x1f;
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/* prepare reg_value for a write */
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tmp |= (dnet->phy_addr << 8);
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tmp |= reg;
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/* write data to write first */
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dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
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/* write control word */
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dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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}
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static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
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{
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u16 value;
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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/* only 5 bits allowed for register offset*/
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reg &= 0x1f;
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/* prepare reg_value for a read */
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value = (dnet->phy_addr << 8);
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value |= reg;
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/* write control word */
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dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
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/* wait for end of transfer */
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
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debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",
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dnet->phy_addr, reg, value);
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return value;
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}
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static int dnet_send(struct eth_device *netdev, void *packet, int length)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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int i, wrsz;
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unsigned int *bufp;
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unsigned int tx_cmd;
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debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length);
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bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
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wrsz = (u32)length + 3;
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wrsz += ((u32)packet) & 0x3;
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wrsz >>= 2;
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tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
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/* check if there is enough room for the current frame */
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if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) {
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for (i = 0; i < wrsz; i++)
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writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
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/*
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* inform MAC that a packet's written and ready
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* to be shipped out
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*/
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writel(tx_cmd, &dnet->regs->TX_LEN_FIFO);
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} else {
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printf(DRIVERNAME "No free space (actual %d, required %d "
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"(words))\n", DNET_FIFO_SIZE -
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readl(&dnet->regs->TX_FIFO_WCNT), wrsz);
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}
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/* No one cares anyway */
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return 0;
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}
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static int dnet_recv(struct eth_device *netdev)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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unsigned int *data_ptr;
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int pkt_len, poll, i;
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u32 cmd_word;
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debug("Waiting for pkt (polling)\n");
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poll = 50;
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while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) {
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udelay(10); /* wait 10 usec */
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if (--poll == 0)
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return 0; /* no pkt available */
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}
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cmd_word = readl(&dnet->regs->RX_LEN_FIFO);
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pkt_len = cmd_word & 0xFFFF;
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debug("Got pkt with size %d bytes\n", pkt_len);
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if (cmd_word & 0xDF180000)
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printf("%s packet receive error %x\n", __func__, cmd_word);
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data_ptr = (unsigned int *)net_rx_packets[0];
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for (i = 0; i < (pkt_len + 3) >> 2; i++)
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*data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO);
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/* ok + 5 ?? */
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net_process_received_packet(net_rx_packets[0], pkt_len + 5);
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return 0;
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}
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static void dnet_set_hwaddr(struct eth_device *netdev)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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u16 tmp;
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tmp = get_unaligned_be16(netdev->enetaddr);
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dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
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tmp = get_unaligned_be16(&netdev->enetaddr[2]);
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dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
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tmp = get_unaligned_be16(&netdev->enetaddr[4]);
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dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
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}
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static void dnet_phy_reset(struct dnet_device *dnet)
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{
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struct eth_device *netdev = &dnet->netdev;
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int i;
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u16 status, adv;
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adv = ADVERTISE_CSMA | ADVERTISE_ALL;
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dnet_mdio_write(dnet, MII_ADVERTISE, adv);
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printf("%s: Starting autonegotiation...\n", netdev->name);
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dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE
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| BMCR_ANRESTART));
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for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
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status = dnet_mdio_read(dnet, MII_BMSR);
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if (status & BMSR_ANEGCOMPLETE)
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break;
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udelay(100);
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}
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if (status & BMSR_ANEGCOMPLETE)
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printf("%s: Autonegotiation complete\n", netdev->name);
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else
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printf("%s: Autonegotiation timed out (status=0x%04x)\n",
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netdev->name, status);
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}
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static int dnet_phy_init(struct dnet_device *dnet)
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{
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struct eth_device *netdev = &dnet->netdev;
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u16 phy_id, status, adv, lpa;
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int media, speed, duplex;
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int i;
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u32 ctl_reg;
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/* Find a PHY */
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for (i = 0; i < 32; i++) {
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dnet->phy_addr = i;
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phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
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if (phy_id != 0xffff) {
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/* ok we found it */
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printf("Found PHY at address %d PHYID (%04x:%04x)\n",
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i, phy_id,
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dnet_mdio_read(dnet, MII_PHYSID2));
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break;
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}
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}
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/* Check if the PHY is up to snuff... */
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phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
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if (phy_id == 0xffff) {
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printf("%s: No PHY present\n", netdev->name);
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return -1;
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}
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status = dnet_mdio_read(dnet, MII_BMSR);
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if (!(status & BMSR_LSTATUS)) {
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/* Try to re-negotiate if we don't have link already. */
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dnet_phy_reset(dnet);
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for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
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status = dnet_mdio_read(dnet, MII_BMSR);
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if (status & BMSR_LSTATUS)
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break;
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udelay(100);
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}
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}
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if (!(status & BMSR_LSTATUS)) {
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printf("%s: link down (status: 0x%04x)\n",
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netdev->name, status);
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return -1;
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} else {
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adv = dnet_mdio_read(dnet, MII_ADVERTISE);
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lpa = dnet_mdio_read(dnet, MII_LPA);
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media = mii_nway_result(lpa & adv);
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
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? 1 : 0);
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duplex = (media & ADVERTISE_FULL) ? 1 : 0;
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/* 1000BaseT ethernet is not supported */
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printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
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netdev->name,
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speed ? "100" : "10",
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duplex ? "full" : "half",
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lpa);
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ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
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if (duplex)
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ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
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else
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ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
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dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
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return 0;
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}
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}
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static int dnet_init(struct eth_device *netdev, struct bd_info *bd)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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u32 config;
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/*
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* dnet_halt should have been called at some point before now,
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* so we'll assume the controller is idle.
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*/
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/* set hardware address */
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dnet_set_hwaddr(netdev);
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if (dnet_phy_init(dnet) < 0)
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return -1;
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/* flush rx/tx fifos */
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writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
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&dnet->regs->SYS_CTL);
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udelay(1000);
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writel(0, &dnet->regs->SYS_CTL);
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config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
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config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
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DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
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DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
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DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
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dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
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/* Enable TX and RX */
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dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,
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DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
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return 0;
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}
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static void dnet_halt(struct eth_device *netdev)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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/* Disable TX and RX */
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dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);
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}
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int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
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{
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struct dnet_device *dnet;
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struct eth_device *netdev;
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unsigned int dev_capa;
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dnet = malloc(sizeof(struct dnet_device));
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if (!dnet) {
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printf("Error: Failed to allocate memory for DNET%d\n", id);
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return -1;
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}
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memset(dnet, 0, sizeof(struct dnet_device));
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netdev = &dnet->netdev;
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dnet->regs = (struct dnet_registers *)regs;
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dnet->phy_addr = phy_addr;
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sprintf(netdev->name, "dnet%d", id);
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netdev->init = dnet_init;
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netdev->halt = dnet_halt;
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netdev->send = dnet_send;
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netdev->recv = dnet_recv;
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dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF;
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debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,
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(dev_capa & DNET_HAS_MDIO) ? "" : "no ",
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(dev_capa & DNET_HAS_IRQ) ? "" : "no ",
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(dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
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(dev_capa & DNET_HAS_DMA) ? "" : "no ");
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eth_register(netdev);
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return 0;
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}
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