132 lines
3.0 KiB
C
132 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#include <dm.h>
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#include <init.h>
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#include <msc01.h>
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#include <pci.h>
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#include <pci_msc01.h>
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#include <asm/io.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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struct msc01_pci_controller {
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struct pci_controller hose;
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void *base;
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};
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static inline struct msc01_pci_controller *
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hose_to_msc01(struct pci_controller *hose)
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{
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return container_of(hose, struct msc01_pci_controller, hose);
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}
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static int msc01_config_access(struct msc01_pci_controller *msc01,
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unsigned char access_type, pci_dev_t bdf,
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int where, u32 *data)
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{
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const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
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void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
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void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
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unsigned int bus = PCI_BUS(bdf);
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unsigned int dev = PCI_DEV(bdf);
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unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
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/* clear abort status */
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__raw_writel(aborts, intstat);
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/* setup address */
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__raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
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(dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
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(devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
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((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
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msc01->base + MSC01_PCI_CFGADDR_OFS);
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/* perform access */
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if (access_type == PCI_ACCESS_WRITE)
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__raw_writel(*data, cfgdata);
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else
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*data = __raw_readl(cfgdata);
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/* check for aborts */
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if (__raw_readl(intstat) & aborts) {
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/* clear abort status */
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__raw_writel(aborts, intstat);
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return -1;
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}
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return 0;
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}
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static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
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uint where, ulong *val, enum pci_size_t size)
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{
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struct msc01_pci_controller *msc01 = dev_get_priv(dev);
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u32 data = 0;
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if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) {
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*val = pci_get_ff(size);
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return 0;
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}
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*val = pci_conv_32_to_size(data, where, size);
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return 0;
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}
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static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
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uint where, ulong val, enum pci_size_t size)
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{
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struct msc01_pci_controller *msc01 = dev_get_priv(dev);
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u32 data = 0;
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if (size == PCI_SIZE_32) {
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data = val;
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} else {
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u32 old;
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if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old))
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return 0;
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data = pci_conv_size_to_32(old, val, where, size);
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}
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msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data);
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return 0;
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}
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static int msc01_pci_probe(struct udevice *dev)
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{
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struct msc01_pci_controller *msc01 = dev_get_priv(dev);
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msc01->base = dev_remap_addr(dev);
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if (!msc01->base)
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return -EINVAL;
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return 0;
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}
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static const struct dm_pci_ops msc01_pci_ops = {
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.read_config = msc01_pci_read_config,
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.write_config = msc01_pci_write_config,
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};
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static const struct udevice_id msc01_pci_ids[] = {
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{ .compatible = "mips,pci-msc01" },
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{ }
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};
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U_BOOT_DRIVER(msc01_pci) = {
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.name = "msc01_pci",
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.id = UCLASS_PCI,
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.of_match = msc01_pci_ids,
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.ops = &msc01_pci_ops,
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.probe = msc01_pci_probe,
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.priv_auto = sizeof(struct msc01_pci_controller),
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};
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