- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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| .. | ||
| Makefile | ||
| init-ld4.c | ||
| init-ld11.c | ||
| init-ld20.c | ||
| init-pro4.c | ||
| init-pro5.c | ||
| init-pxs2.c | ||
| init-sld3.c | ||
| init-sld8.c | ||
| init.c | ||