549 lines
16 KiB
C
549 lines
16 KiB
C
/*
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* Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
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* Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <common.h>
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#include <config.h>
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#include <nand.h>
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/* registers */
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#define NFC_CTL 0x00000000
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#define NFC_ST 0x00000004
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#define NFC_INT 0x00000008
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#define NFC_TIMING_CTL 0x0000000C
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#define NFC_TIMING_CFG 0x00000010
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#define NFC_ADDR_LOW 0x00000014
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#define NFC_ADDR_HIGH 0x00000018
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#define NFC_SECTOR_NUM 0x0000001C
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#define NFC_CNT 0x00000020
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#define NFC_CMD 0x00000024
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#define NFC_RCMD_SET 0x00000028
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#define NFC_WCMD_SET 0x0000002C
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#define NFC_IO_DATA 0x00000030
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#define NFC_ECC_CTL 0x00000034
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#define NFC_ECC_ST 0x00000038
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#define NFC_DEBUG 0x0000003C
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#define NFC_ECC_CNT0 0x00000040
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#define NFC_ECC_CNT1 0x00000044
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#define NFC_ECC_CNT2 0x00000048
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#define NFC_ECC_CNT3 0x0000004C
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#define NFC_USER_DATA_BASE 0x00000050
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#define NFC_EFNAND_STATUS 0x00000090
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#define NFC_SPARE_AREA 0x000000A0
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#define NFC_PATTERN_ID 0x000000A4
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#define NFC_RAM0_BASE 0x00000400
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#define NFC_RAM1_BASE 0x00000800
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#define NFC_CTL_EN (1 << 0)
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#define NFC_CTL_RESET (1 << 1)
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#define NFC_CTL_RAM_METHOD (1 << 14)
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#define NFC_CTL_PAGE_SIZE_MASK (0xf << 8)
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#define NFC_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
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#define NFC_ECC_EN (1 << 0)
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#define NFC_ECC_PIPELINE (1 << 3)
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#define NFC_ECC_EXCEPTION (1 << 4)
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#define NFC_ECC_BLOCK_SIZE (1 << 5)
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#define NFC_ECC_RANDOM_EN (1 << 9)
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#define NFC_ECC_RANDOM_DIRECTION (1 << 10)
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#define NFC_ADDR_NUM_OFFSET 16
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#define NFC_SEND_ADR (1 << 19)
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#define NFC_ACCESS_DIR (1 << 20)
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#define NFC_DATA_TRANS (1 << 21)
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#define NFC_SEND_CMD1 (1 << 22)
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#define NFC_WAIT_FLAG (1 << 23)
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#define NFC_SEND_CMD2 (1 << 24)
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#define NFC_SEQ (1 << 25)
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#define NFC_DATA_SWAP_METHOD (1 << 26)
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#define NFC_ROW_AUTO_INC (1 << 27)
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#define NFC_SEND_CMD3 (1 << 28)
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#define NFC_SEND_CMD4 (1 << 29)
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#define NFC_RAW_CMD (0 << 30)
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#define NFC_PAGE_CMD (2 << 30)
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#define NFC_ST_CMD_INT_FLAG (1 << 1)
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#define NFC_ST_DMA_INT_FLAG (1 << 2)
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#define NFC_READ_CMD_OFFSET 0
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#define NFC_RANDOM_READ_CMD0_OFFSET 8
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#define NFC_RANDOM_READ_CMD1_OFFSET 16
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#define NFC_CMD_RNDOUTSTART 0xE0
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#define NFC_CMD_RNDOUT 0x05
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#define NFC_CMD_READSTART 0x30
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#define SUNXI_DMA_CFG_REG0 0x300
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#define SUNXI_DMA_SRC_START_ADDR_REG0 0x304
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#define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
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#define SUNXI_DMA_DDMA_BC_REG0 0x30C
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#define SUNXI_DMA_DDMA_PARA_REG0 0x318
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#define SUNXI_DMA_DDMA_CFG_REG_LOADING (1 << 31)
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#define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
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#define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
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#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
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#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
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#define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
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#define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
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#define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
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struct nfc_config {
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int page_size;
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int ecc_strength;
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int ecc_size;
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int addr_cycles;
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int nseeds;
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bool randomize;
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bool valid;
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};
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/* minimal "boot0" style NAND support for Allwinner A20 */
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/* random seed used by linux */
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const uint16_t random_seed[128] = {
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0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
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0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
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0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
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0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
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0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
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0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
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0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
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0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
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0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
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0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
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0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
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0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
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0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
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0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
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0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
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0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
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};
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#define DEFAULT_TIMEOUT_US 100000
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static int check_value_inner(int offset, int expected_bits,
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int timeout_us, int negation)
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{
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do {
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int val = readl(offset) & expected_bits;
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if (negation ? !val : val)
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return 1;
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udelay(1);
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} while (--timeout_us);
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return 0;
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}
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static inline int check_value(int offset, int expected_bits,
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int timeout_us)
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{
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return check_value_inner(offset, expected_bits, timeout_us, 0);
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}
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static inline int check_value_negated(int offset, int unexpected_bits,
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int timeout_us)
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{
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return check_value_inner(offset, unexpected_bits, timeout_us, 1);
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}
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void nand_init(void)
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{
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uint32_t val;
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board_nand_init();
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val = readl(SUNXI_NFC_BASE + NFC_CTL);
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/* enable and reset CTL */
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writel(val | NFC_CTL_EN | NFC_CTL_RESET,
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SUNXI_NFC_BASE + NFC_CTL);
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if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
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NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
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printf("Couldn't initialize nand\n");
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}
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/* reset NAND */
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writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
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writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
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SUNXI_NFC_BASE + NFC_CMD);
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if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
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DEFAULT_TIMEOUT_US)) {
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printf("Error timeout waiting for nand reset\n");
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return;
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}
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writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
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}
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static void nand_apply_config(const struct nfc_config *conf)
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{
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u32 val;
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val = readl(SUNXI_NFC_BASE + NFC_CTL);
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val &= ~NFC_CTL_PAGE_SIZE_MASK;
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writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
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SUNXI_NFC_BASE + NFC_CTL);
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writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
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writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);
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}
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static int nand_load_page(const struct nfc_config *conf, u32 offs)
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{
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int page = offs / conf->page_size;
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writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
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(NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
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(NFC_CMD_READSTART << NFC_READ_CMD_OFFSET),
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SUNXI_NFC_BASE + NFC_RCMD_SET);
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writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
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writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
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writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
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writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | NFC_WAIT_FLAG |
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((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR,
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SUNXI_NFC_BASE + NFC_CMD);
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if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
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DEFAULT_TIMEOUT_US)) {
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printf("Error while initializing dma interrupt\n");
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return -EIO;
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}
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return 0;
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}
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static int nand_reset_column(void)
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{
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writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
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(NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
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(NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET),
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SUNXI_NFC_BASE + NFC_RCMD_SET);
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writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW);
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writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
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(1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR | NFC_CMD_RNDOUT,
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SUNXI_NFC_BASE + NFC_CMD);
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if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
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DEFAULT_TIMEOUT_US)) {
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printf("Error while initializing dma interrupt\n");
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return -1;
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}
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return 0;
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}
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static int nand_read_page(const struct nfc_config *conf, u32 offs,
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void *dest, int len)
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{
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dma_addr_t dst = (dma_addr_t)dest;
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int nsectors = len / conf->ecc_size;
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u16 rand_seed;
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u32 val;
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int page;
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page = offs / conf->page_size;
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if (offs % conf->page_size || len % conf->ecc_size ||
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len > conf->page_size || len < 0)
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return -EINVAL;
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/* clear ecc status */
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writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
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/* Choose correct seed */
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rand_seed = random_seed[page % conf->nseeds];
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writel((rand_seed << 16) | (conf->ecc_strength << 12) |
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(conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
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(conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
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NFC_ECC_EN | NFC_ECC_PIPELINE | NFC_ECC_EXCEPTION,
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SUNXI_NFC_BASE + NFC_ECC_CTL);
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flush_dcache_range(dst, ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
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/* SUNXI_DMA */
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writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
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/* read from REG_IO_DATA */
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writel(SUNXI_NFC_BASE + NFC_IO_DATA,
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SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
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/* read to RAM */
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writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
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writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC |
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SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
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SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
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writel(len, SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0);
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writel(SUNXI_DMA_DDMA_CFG_REG_LOADING |
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SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 |
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SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM |
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SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 |
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SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO |
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SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
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SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
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writel(nsectors, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
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writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
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writel(NFC_DATA_TRANS | NFC_PAGE_CMD | NFC_DATA_SWAP_METHOD,
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SUNXI_NFC_BASE + NFC_CMD);
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if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
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DEFAULT_TIMEOUT_US)) {
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printf("Error while initializing dma interrupt\n");
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return -EIO;
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}
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writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
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if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
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SUNXI_DMA_DDMA_CFG_REG_LOADING,
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DEFAULT_TIMEOUT_US)) {
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printf("Error while waiting for dma transfer to finish\n");
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return -EIO;
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}
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invalidate_dcache_range(dst,
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ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
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val = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
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/* ECC error detected. */
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if (val & 0xffff)
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return -EIO;
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/*
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* Return 1 if the page is empty.
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* We consider the page as empty if the first ECC block is marked
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* empty.
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*/
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return (val & 0x10000) ? 1 : 0;
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}
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static int nand_max_ecc_strength(struct nfc_config *conf)
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{
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static const int ecc_bytes[] = { 32, 46, 54, 60, 74, 88, 102, 110, 116 };
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int max_oobsize, max_ecc_bytes;
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int nsectors = conf->page_size / conf->ecc_size;
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int i;
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/*
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* ECC strength is limited by the size of the OOB area which is
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* correlated with the page size.
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*/
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switch (conf->page_size) {
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case 2048:
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max_oobsize = 64;
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break;
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case 4096:
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max_oobsize = 256;
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break;
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case 8192:
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max_oobsize = 640;
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break;
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case 16384:
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max_oobsize = 1664;
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break;
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default:
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return -EINVAL;
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}
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max_ecc_bytes = max_oobsize / nsectors;
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for (i = 0; i < ARRAY_SIZE(ecc_bytes); i++) {
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if (ecc_bytes[i] > max_ecc_bytes)
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break;
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}
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if (!i)
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return -EINVAL;
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return i - 1;
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}
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static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs,
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void *dest)
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{
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/* NAND with pages > 4k will likely require 1k sector size. */
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int min_ecc_size = conf->page_size > 4096 ? 1024 : 512;
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int page = offs / conf->page_size;
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int ret;
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/*
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* In most cases, 1k sectors are preferred over 512b ones, start
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* testing this config first.
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*/
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for (conf->ecc_size = 1024; conf->ecc_size >= min_ecc_size;
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conf->ecc_size >>= 1) {
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int max_ecc_strength = nand_max_ecc_strength(conf);
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nand_apply_config(conf);
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/*
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* We are starting from the maximum ECC strength because
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* most of the time NAND vendors provide an OOB area that
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* barely meets the ECC requirements.
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*/
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for (conf->ecc_strength = max_ecc_strength;
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conf->ecc_strength >= 0;
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conf->ecc_strength--) {
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conf->randomize = false;
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if (nand_reset_column())
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return -EIO;
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/*
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* Only read the first sector to speedup detection.
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*/
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ret = nand_read_page(conf, offs, dest, conf->ecc_size);
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if (!ret) {
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return 0;
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} else if (ret > 0) {
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/*
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* If page is empty we can't deduce anything
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* about the ECC config => stop the detection.
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*/
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return -EINVAL;
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}
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conf->randomize = true;
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conf->nseeds = ARRAY_SIZE(random_seed);
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do {
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if (nand_reset_column())
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return -EIO;
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if (!nand_read_page(conf, offs, dest,
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conf->ecc_size))
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return 0;
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/*
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* Find the next ->nseeds value that would
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* change the randomizer seed for the page
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* we're trying to read.
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*/
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while (conf->nseeds >= 16) {
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int seed = page % conf->nseeds;
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|
conf->nseeds >>= 1;
|
|
if (seed != page % conf->nseeds)
|
|
break;
|
|
}
|
|
} while (conf->nseeds >= 16);
|
|
}
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest)
|
|
{
|
|
if (conf->valid)
|
|
return 0;
|
|
|
|
/*
|
|
* Modern NANDs are more likely than legacy ones, so we start testing
|
|
* with 5 address cycles.
|
|
*/
|
|
for (conf->addr_cycles = 5;
|
|
conf->addr_cycles >= 4;
|
|
conf->addr_cycles--) {
|
|
int max_page_size = conf->addr_cycles == 4 ? 2048 : 16384;
|
|
|
|
/*
|
|
* Ignoring 1k pages cause I'm not even sure this case exist
|
|
* in the real world.
|
|
*/
|
|
for (conf->page_size = 2048; conf->page_size <= max_page_size;
|
|
conf->page_size <<= 1) {
|
|
if (nand_load_page(conf, offs))
|
|
return -1;
|
|
|
|
if (!nand_detect_ecc_config(conf, offs, dest)) {
|
|
conf->valid = true;
|
|
return 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int nand_read_buffer(struct nfc_config *conf, uint32_t offs,
|
|
unsigned int size, void *dest)
|
|
{
|
|
int first_seed, page, ret;
|
|
|
|
size = ALIGN(size, conf->page_size);
|
|
page = offs / conf->page_size;
|
|
first_seed = page % conf->nseeds;
|
|
|
|
for (; size; size -= conf->page_size) {
|
|
if (nand_load_page(conf, offs))
|
|
return -1;
|
|
|
|
ret = nand_read_page(conf, offs, dest, conf->page_size);
|
|
/*
|
|
* The ->nseeds value should be equal to the number of pages
|
|
* in an eraseblock. Since we don't know this information in
|
|
* advance we might have picked a wrong value.
|
|
*/
|
|
if (ret < 0 && conf->randomize) {
|
|
int cur_seed = page % conf->nseeds;
|
|
|
|
/*
|
|
* We already tried all the seed values => we are
|
|
* facing a real corruption.
|
|
*/
|
|
if (cur_seed < first_seed)
|
|
return -EIO;
|
|
|
|
/* Try to adjust ->nseeds and read the page again... */
|
|
conf->nseeds = cur_seed;
|
|
|
|
if (nand_reset_column())
|
|
return -EIO;
|
|
|
|
/* ... it still fails => it's a real corruption. */
|
|
if (nand_read_page(conf, offs, dest, conf->page_size))
|
|
return -EIO;
|
|
} else if (ret && conf->randomize) {
|
|
memset(dest, 0xff, conf->page_size);
|
|
}
|
|
|
|
page++;
|
|
offs += conf->page_size;
|
|
dest += conf->page_size;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
|
|
{
|
|
static struct nfc_config conf = { };
|
|
int ret;
|
|
|
|
ret = nand_detect_config(&conf, offs, dest);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return nand_read_buffer(&conf, offs, size, dest);
|
|
}
|
|
|
|
void nand_deselect(void)
|
|
{
|
|
struct sunxi_ccm_reg *const ccm =
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
|
|
#ifdef CONFIG_MACH_SUN9I
|
|
clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
|
|
#else
|
|
clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
|
|
#endif
|
|
clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
|
|
}
|