74 lines
1.2 KiB
Plaintext
74 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP R5
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*
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* (C) Copyright 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynqmp-r5";
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model = "Xilinx ZynqMP R5";
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cpu@0 {
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compatible = "arm,cortex-r5";
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device_type = "cpu";
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart1;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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chosen {
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bootargs = "";
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stdout-path = "serial0:115200n8";
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};
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clk100: clk100 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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u-boot,dm-pre-reloc;
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};
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amba {
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u-boot,dm-pre-reloc;
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ttc0: timer@ff110000 {
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compatible = "cdns,ttc";
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status = "okay";
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reg = <0xff110000 0x1000>;
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timer-width = <32>;
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clocks = <&clk100>;
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};
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uart1: serial@ff010000 {
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u-boot,dm-pre-reloc;
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compatible = "cdns,uart-r1p12", "xlnx,xuartps";
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reg = <0xff010000 0x1000>;
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clock-names = "uart_clk", "pclk";
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clocks = <&clk100 &clk100>;
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};
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};
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};
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