270 lines
8.9 KiB
Plaintext
270 lines
8.9 KiB
Plaintext
Intro:
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======
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The SBC8548 is a stand alone single board computer with a 1GHz
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MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
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memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
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and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
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ethernet connections.
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U-boot Configuration:
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=====================
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The following possible u-boot configuration targets are available:
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1) sbc8548_config
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2) sbc8548_PCI_33_config
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3) sbc8548_PCI_66_config
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4) sbc8548_PCI_33_PCIE_config
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5) sbc8548_PCI_66_PCIE_config
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Generally speaking, most people should choose to use #5. Details
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of each choice are listed below.
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Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
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will be left empty (M66EN high), and so the board will operate with
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a base clock of 66MHz. Note that you need both PCI enabled in u-boot
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and linux in order to have functional PCI under linux.
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The second enables PCI support and builds for a 33MHz clock rate. Note
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that if a 33MHz 32bit card is inserted in the slot, then the whole board
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will clock down to a 33MHz base clock instead of the default 66MHz. This
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will change the baud clocks and mess up your serial console output if you
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were previously running at 66MHz. If you want to use a 33MHz PCI card,
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then you should build a U-Boot with a _PCI_33_ config and store this
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to flash prior to powering down the board and inserting the 33MHz PCI
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card. [The above discussion assumes that the SW2[1-4] has not been changed
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to reflect a different CCB:SYSCLK ratio]
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The third option builds PCI support in, and leaves the clocking at the
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default 66MHz. Options four and five are just repeats of option two
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and three, but with PCI-e support enabled as well.
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PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
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is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
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a 33MHz PCI configuration is currently untested.)
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=> pci 0
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Scanning PCI devices on bus 0
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BusDevFun VendorId DeviceId Device Class Sub-Class
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_____________________________________________________________
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00.00.00 0x1057 0x0012 Processor 0x20
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00.01.00 0x8086 0x1026 Network controller 0x00
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=> pci 1
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Scanning PCI devices on bus 1
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BusDevFun VendorId DeviceId Device Class Sub-Class
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_____________________________________________________________
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01.00.00 0x1957 0x0012 Processor 0x20
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=> pci 2
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Scanning PCI devices on bus 2
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BusDevFun VendorId DeviceId Device Class Sub-Class
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_____________________________________________________________
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02.00.00 0x1148 0x9e00 Network controller 0x00
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=>
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Memory Size and using SPD:
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==========================
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The default configuration uses hard coded memory configuration settings
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for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
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EEPROM data to read what memory is installed.
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There is a hardware errata, which causes the older local bus SDRAM
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SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
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that the SPD data can not be read reliably. You can test if your
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board has the errata fix by running "i2c probe". If you see 0x53
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as a valid device, it has been fixed. If you only see 0x50, 0x51
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then your board does not have the fix.
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You can also visually inspect the board to see if this hardware
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fix has been applied:
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1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
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the back of the PCB behind the DDR SDRAM SODIMM connector.
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2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
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to R313 pin 2. Pin 2 for each resistor is the end of the
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resistor closest to the CPU.
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Boards without the mod will have R314 and R313 in parallel, like "||".
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After the mod, they will be touching and form an "L" shape.
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If you want to upgrade to larger RAM size, you can simply enable
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#define CONFIG_SPD_EEPROM
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#define CONFIG_DDR_SPD
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in include/configs/sbc8548.h file. (The lines are already there
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but listed as #undef).
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If you did the i2c test, and your board does not have the errata
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fix, then you will have to physically remove the LBC 128MB DIMM
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from the board's socket to resolve the above i2c address overlap
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issue and allow SPD autodetection of RAM to work.
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Updating U-boot with U-boot:
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============================
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Note that versions of u-boot up to and including 2009.08 had u-boot stored
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at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
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0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
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update u-boot with u-boot and it uses the old address, you will render
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your board inoperable, and you will require JTAG recovery.
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The following steps list how to update with the current address:
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tftp u-boot.bin
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md 200000 10
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protect off all
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erase fffa0000 ffffffff
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cp.b 200000 fffa0000 60000
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md fffa0000 10
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protect on all
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The "md" steps in the above are just a precautionary step that allow
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you to confirm the u-boot version that was downloaded, and then confirm
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that it was copied to flash.
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The above assumes that you are using the default board settings which
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have u-boot in the 8MB flash, tied to /CS0.
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If you are running the default 8MB /CS0 settings but want to store an
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image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
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(as a backup, etc) then the steps will become:
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tftp u-boot.bin
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md 200000 10
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protect off all
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era eff00000 efffffff
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cp.b 200000 eff00000 100000
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md eff00000 10
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protect on all
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Finally, if you are running the alternate 64MB /CS0 settings and want
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to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
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enabled) the steps will become:
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tftp u-boot.bin
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md 200000 10
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protect off all
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era fff00000 ffffffff
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cp.b 200000 fff00000 100000
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md fff00000 10
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protect on all
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Hardware Reference:
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===================
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The following contains some summary information on hardware settings
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that are relevant to u-boot, based on the board manual. For the
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most up to date and complete details of the board, please request the
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reference manual ERG-00327-001.pdf from www.windriver.com
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Boot flash:
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intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
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Sodimm flash:
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intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
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Note that this address reflects the default setting for
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the JTAG debugging tools, but since the alignment is
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rather inconvenient, u-boot puts it at 0xec00_0000.
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Jumpers:
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Jumper Name ON OFF
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----------------------------------------------------------------
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JP12 CS0/CS6 swap see note[*] see note[*]
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JP13 SODIMM flash write OK writes disabled
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write prot.
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JP14 HRESET/TRST joined isolated
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JP15 PWR ON when AC pwr use S1 for on/off
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JP16 Demo LEDs lit not lit
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JP19 PCI mode PCI PCI-X
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[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
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onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
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is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
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SODIMM flash and /CS6 is for the boot flash. Note that in this
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alternate setting, you also need to switch SW2.8 to ON.
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See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
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and boot u-boot from the 64MB SODIMM
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Switches:
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The defaults are marked with a *
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Name Desc. ON OFF
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------------------------------------------------------------------
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S1 Pwr toggle n/a n/a
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SW2.1 CFG_SYS_PLL0 1 0*
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SW2.2 CFG_SYS_PLL1 1* 0
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SW2.3 CFG_SYS_PLL2 1* 0
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SW2.4 CFG_SYS_PLL3 1 0*
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SW2.5 CFG_CORE_PLL0 1* 0
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SW2.6 CFG_CORE_PLL1 1 0*
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SW2.7 CFG_CORE_PLL2 1* 0
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SW2.8 CFG_ROM_LOC1 1 0*
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SW3.1 CFG_HOST_AGT0 1* 0
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SW3.2 CFG_HOST_AGT1 1* 0
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SW3.3 CFG_HOST_AGT2 1* 0
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SW3.4 CFG_IO_PORTS0 1* 0
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SW3.5 CFG_IO_PORTS0 1 0*
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SW3.6 CFG_IO_PORTS0 1 0*
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SerDes CLK(MHz) SW5.1 SW5.2
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----------------------------------------------
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25 0 0
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100* 1 0
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125 0 1
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200 1 1
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SerDes CLK spread SW5.3 SW5.4
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----------------------------------------------
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+/- 0.25% 0 0
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-0.50% 1 0
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-0.75% 0 1
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No Spread* 1 1
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SW4 settings are readable from the EPLD and are currently not used for
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any hardware settings (i.e. user configuration switches).
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LEDs:
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Name Desc. ON OFF
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------------------------------------------------------------------
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D13 PCI/PCI-X PCI-X PCI
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D14 3.3V PWR 3.3V no power
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D15 SYSCLK 66MHz 33MHz
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Default Memory Map:
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start end CS<n> width Desc.
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----------------------------------------------------------------------
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0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
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f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
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f800_0000 f8b0_1fff CS5 - EPLD
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fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
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ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
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[*] fb80 represents the default programmed by WR JTAG register files,
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but u-boot places the flash at either ec00 or fc00 based on JP12.
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The EPLD on CS5 demuxes the following devices at the following offsets:
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offset size width device
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--------------------------------------------------------
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0 1fff 8 7 segment display LED
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10_0000 1fff 4 user switches
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30_0000 1fff 4 HW Rev. register
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b0_0000 1fff 8 8kB EEPROM
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