210 lines
5.9 KiB
C
210 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Typedefs and defines for working with Octeon physical addresses.
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*/
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#ifndef __CVMX_ADDRESS_H__
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#define __CVMX_ADDRESS_H__
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typedef enum {
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CVMX_MIPS_SPACE_XKSEG = 3LL,
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CVMX_MIPS_SPACE_XKPHYS = 2LL,
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CVMX_MIPS_SPACE_XSSEG = 1LL,
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CVMX_MIPS_SPACE_XUSEG = 0LL
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} cvmx_mips_space_t;
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typedef enum {
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CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
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CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
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CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
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CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
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} cvmx_mips_xkseg_space_t;
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/* decodes <14:13> of a kseg3 window address */
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typedef enum {
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CVMX_ADD_WIN_SCR = 0L,
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CVMX_ADD_WIN_DMA = 1L,
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CVMX_ADD_WIN_UNUSED = 2L,
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CVMX_ADD_WIN_UNUSED2 = 3L
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} cvmx_add_win_dec_t;
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/* decode within DMA space */
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typedef enum {
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CVMX_ADD_WIN_DMA_ADD = 0L,
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CVMX_ADD_WIN_DMA_SENDMEM = 1L,
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/* store data must be normal DRAM memory space address in this case */
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CVMX_ADD_WIN_DMA_SENDDMA = 2L,
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/* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
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CVMX_ADD_WIN_DMA_SENDIO = 3L,
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/* store data must be normal IO space address in this case */
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CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
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/* no write buffer data needed/used */
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} cvmx_add_win_dma_dec_t;
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/**
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* Physical Address Decode
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*
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* Octeon-I HW never interprets this X (<39:36> reserved
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* for future expansion), software should set to 0.
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*
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* - 0x0 XXX0 0000 0000 to DRAM Cached
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* - 0x0 XXX0 0FFF FFFF
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*
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* - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
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* - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
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*
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* - 0x0 XXX0 2000 0000 to DRAM Cached
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* - 0x0 XXXF FFFF FFFF
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*
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* - 0x1 00X0 0000 0000 to Boot Bus Uncached
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* - 0x1 00XF FFFF FFFF
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*
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* - 0x1 01X0 0000 0000 to Other NCB Uncached
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* - 0x1 FFXF FFFF FFFF devices
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*
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* Decode of all Octeon addresses
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*/
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typedef union {
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u64 u64;
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struct {
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cvmx_mips_space_t R : 2;
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u64 offset : 62;
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} sva;
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struct {
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u64 zeroes : 33;
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u64 offset : 31;
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} suseg;
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struct {
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u64 ones : 33;
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cvmx_mips_xkseg_space_t sp : 2;
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u64 offset : 29;
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} sxkseg;
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struct {
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cvmx_mips_space_t R : 2;
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u64 cca : 3;
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u64 mbz : 10;
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u64 pa : 49;
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} sxkphys;
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struct {
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u64 mbz : 15;
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u64 is_io : 1;
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u64 did : 8;
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u64 unaddr : 4;
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u64 offset : 36;
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} sphys;
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struct {
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u64 zeroes : 24;
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u64 unaddr : 4;
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u64 offset : 36;
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} smem;
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struct {
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u64 mem_region : 2;
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u64 mbz : 13;
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u64 is_io : 1;
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u64 did : 8;
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u64 unaddr : 4;
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u64 offset : 36;
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} sio;
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struct {
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u64 ones : 49;
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cvmx_add_win_dec_t csrdec : 2;
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u64 addr : 13;
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} sscr;
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/* there should only be stores to IOBDMA space, no loads */
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struct {
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u64 ones : 49;
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cvmx_add_win_dec_t csrdec : 2;
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u64 unused2 : 3;
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cvmx_add_win_dma_dec_t type : 3;
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u64 addr : 7;
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} sdma;
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struct {
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u64 didspace : 24;
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u64 unused : 40;
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} sfilldidspace;
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} cvmx_addr_t;
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/* These macros for used by 32 bit applications */
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#define CVMX_MIPS32_SPACE_KSEG0 1l
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#define CVMX_ADD_SEG32(segment, add) (((s32)segment << 31) | (s32)(add))
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/*
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* Currently all IOs are performed using XKPHYS addressing. Linux uses the
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* CvmMemCtl register to enable XKPHYS addressing to IO space from user mode.
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* Future OSes may need to change the upper bits of IO addresses. The
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* following define controls the upper two bits for all IO addresses generated
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* by the simple executive library
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*/
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#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
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/* These macros simplify the process of creating common IO addresses */
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#define CVMX_ADD_SEG(segment, add) ((((u64)segment) << 62) | (add))
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#define CVMX_ADD_IO_SEG(add) (add)
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#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
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#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
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#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
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/* from include/ncb_rsl_id.v */
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#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
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#define CVMX_OCT_DID_GMX0 1ULL
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#define CVMX_OCT_DID_GMX1 2ULL
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#define CVMX_OCT_DID_PCI 3ULL
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#define CVMX_OCT_DID_KEY 4ULL
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#define CVMX_OCT_DID_FPA 5ULL
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#define CVMX_OCT_DID_DFA 6ULL
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#define CVMX_OCT_DID_ZIP 7ULL
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#define CVMX_OCT_DID_RNG 8ULL
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#define CVMX_OCT_DID_IPD 9ULL
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#define CVMX_OCT_DID_PKT 10ULL
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#define CVMX_OCT_DID_TIM 11ULL
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#define CVMX_OCT_DID_TAG 12ULL
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/* the rest are not on the IO bus */
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#define CVMX_OCT_DID_L2C 16ULL
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#define CVMX_OCT_DID_LMC 17ULL
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#define CVMX_OCT_DID_SPX0 18ULL
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#define CVMX_OCT_DID_SPX1 19ULL
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#define CVMX_OCT_DID_PIP 20ULL
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#define CVMX_OCT_DID_ASX0 22ULL
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#define CVMX_OCT_DID_ASX1 23ULL
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#define CVMX_OCT_DID_IOB 30ULL
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#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
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#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
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#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
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#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
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#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
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#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
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#define CVMX_OCT_DID_TAG_TAG5 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 5ULL)
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#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
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#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
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#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
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#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
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#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
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#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
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#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
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#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
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#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
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#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
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#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
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/* Cast to unsigned long long, mainly for use in printfs. */
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#define CAST_ULL(v) ((unsigned long long)(v))
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#define UNMAPPED_PTR(x) ((1ULL << 63) | (x))
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#endif /* __CVMX_ADDRESS_H__ */
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