607 lines
19 KiB
C
607 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Interface to the hardware Fetch and Add Unit.
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*/
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/**
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* @file
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*
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* Interface to the hardware Fetch and Add Unit.
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*
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*/
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#ifndef __CVMX_HWFAU_H__
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#define __CVMX_HWFAU_H__
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typedef int cvmx_fau_reg64_t;
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typedef int cvmx_fau_reg32_t;
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typedef int cvmx_fau_reg16_t;
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typedef int cvmx_fau_reg8_t;
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#define CVMX_FAU_REG_ANY -1
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/*
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* Octeon Fetch and Add Unit (FAU)
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*/
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#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0)
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#define CVMX_FAU_BITS_SCRADDR 63, 56
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#define CVMX_FAU_BITS_LEN 55, 48
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#define CVMX_FAU_BITS_INEVAL 35, 14
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#define CVMX_FAU_BITS_TAGWAIT 13, 13
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#define CVMX_FAU_BITS_NOADD 13, 13
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#define CVMX_FAU_BITS_SIZE 12, 11
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#define CVMX_FAU_BITS_REGISTER 10, 0
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#define CVMX_FAU_MAX_REGISTERS_8 (2048)
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typedef enum {
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CVMX_FAU_OP_SIZE_8 = 0,
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CVMX_FAU_OP_SIZE_16 = 1,
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CVMX_FAU_OP_SIZE_32 = 2,
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CVMX_FAU_OP_SIZE_64 = 3
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} cvmx_fau_op_size_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct {
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u64 error : 1;
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s64 value : 63;
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} cvmx_fau_tagwait64_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct {
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u64 error : 1;
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s32 value : 31;
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} cvmx_fau_tagwait32_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct {
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u64 error : 1;
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s16 value : 15;
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} cvmx_fau_tagwait16_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct {
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u64 error : 1;
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int8_t value : 7;
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} cvmx_fau_tagwait8_t;
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/**
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* Asynchronous tagwait return definition. If a timeout occurs,
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* the error bit will be set. Otherwise the value of the
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* register before the update will be returned.
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*/
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typedef union {
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u64 u64;
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struct {
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u64 invalid : 1;
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u64 data : 63; /* unpredictable if invalid is set */
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} s;
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} cvmx_fau_async_tagwait_result_t;
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#define SWIZZLE_8 0
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#define SWIZZLE_16 0
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#define SWIZZLE_32 0
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/**
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* @INTERNAL
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* Builds a store I/O address for writing to the FAU
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*
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* @param noadd 0 = Store value is atomically added to the current value
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* 1 = Store value is atomically written over the current value
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* @return Address to store for atomic update
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*/
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static inline u64 __cvmx_hwfau_store_address(u64 noadd, u64 reg)
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{
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return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
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cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
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}
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/**
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* @INTERNAL
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* Builds a I/O address for accessing the FAU
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*
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* @param tagwait Should the atomic add wait for the current tag switch
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* operation to complete.
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* - 0 = Don't wait
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* - 1 = Wait for tag switch to complete
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: When performing 32 and 64 bit access, only the low
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* 22 bits are available.
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* @return Address to read from for atomic update
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*/
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static inline u64 __cvmx_hwfau_atomic_address(u64 tagwait, u64 reg, s64 value)
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{
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return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
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cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
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cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
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}
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/**
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* Perform an atomic 64 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline s64 cvmx_hwfau_fetch_and_add64(cvmx_fau_reg64_t reg, s64 value)
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{
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return cvmx_read64_int64(__cvmx_hwfau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 32 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline s32 cvmx_hwfau_fetch_and_add32(cvmx_fau_reg32_t reg, s32 value)
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{
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reg ^= SWIZZLE_32;
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return cvmx_read64_int32(__cvmx_hwfau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 16 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline s16 cvmx_hwfau_fetch_and_add16(cvmx_fau_reg16_t reg, s16 value)
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{
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reg ^= SWIZZLE_16;
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return cvmx_read64_int16(__cvmx_hwfau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 8 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline int8_t cvmx_hwfau_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value)
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{
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reg ^= SWIZZLE_8;
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return cvmx_read64_int8(__cvmx_hwfau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 64 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait64_t cvmx_hwfau_tagwait_fetch_and_add64(cvmx_fau_reg64_t reg,
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s64 value)
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{
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union {
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u64 i64;
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cvmx_fau_tagwait64_t t;
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} result;
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result.i64 = cvmx_read64_int64(__cvmx_hwfau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* Perform an atomic 32 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait32_t cvmx_hwfau_tagwait_fetch_and_add32(cvmx_fau_reg32_t reg,
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s32 value)
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{
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union {
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u64 i32;
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cvmx_fau_tagwait32_t t;
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} result;
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reg ^= SWIZZLE_32;
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result.i32 = cvmx_read64_int32(__cvmx_hwfau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* Perform an atomic 16 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait16_t cvmx_hwfau_tagwait_fetch_and_add16(cvmx_fau_reg16_t reg,
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s16 value)
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{
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union {
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u64 i16;
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cvmx_fau_tagwait16_t t;
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} result;
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reg ^= SWIZZLE_16;
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result.i16 = cvmx_read64_int16(__cvmx_hwfau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* Perform an atomic 8 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait8_t cvmx_hwfau_tagwait_fetch_and_add8(cvmx_fau_reg8_t reg,
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int8_t value)
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{
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union {
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u64 i8;
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cvmx_fau_tagwait8_t t;
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} result;
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reg ^= SWIZZLE_8;
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result.i8 = cvmx_read64_int8(__cvmx_hwfau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* @INTERNAL
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* Builds I/O data for async operations
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*
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* @param scraddr Scratch pad byte address to write to. Must be 8 byte aligned
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* @param value Signed value to add.
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* Note: When performing 32 and 64 bit access, only the low
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* 22 bits are available.
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* @param tagwait Should the atomic add wait for the current tag switch
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* operation to complete.
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* - 0 = Don't wait
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* - 1 = Wait for tag switch to complete
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* @param size The size of the operation:
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* - CVMX_FAU_OP_SIZE_8 (0) = 8 bits
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* - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
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* - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
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* - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* @return Data to write using cvmx_send_single
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*/
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static inline u64 __cvmx_fau_iobdma_data(u64 scraddr, s64 value, u64 tagwait,
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cvmx_fau_op_size_t size, u64 reg)
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{
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return (CVMX_FAU_LOAD_IO_ADDRESS | cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
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cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
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cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
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cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
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cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
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}
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/**
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* Perform an async atomic 64 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_hwfau_async_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, s64 value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
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}
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/**
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* Perform an async atomic 32 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_hwfau_async_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, s32 value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
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}
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/**
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* Perform an async atomic 16 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_hwfau_async_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, s16 value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
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}
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/**
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* Perform an async atomic 8 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_hwfau_async_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
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}
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/**
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* Perform an async atomic 64 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
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* the value of the register before the update will be
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* returned
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_hwfau_async_tagwait_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg,
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s64 value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
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}
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/**
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* Perform an async atomic 32 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
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* the value of the register before the update will be
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* returned
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_hwfau_async_tagwait_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg,
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s32 value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
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}
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/**
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* Perform an async atomic 16 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
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* the value of the register before the update will be
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* returned
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_hwfau_async_tagwait_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg,
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s16 value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
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}
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/**
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* Perform an async atomic 8 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
|
|
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
|
* the value of the register before the update will be
|
|
* returned
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* @param value Signed value to add.
|
|
* @return Placed in the scratch pad register
|
|
*/
|
|
static inline void cvmx_hwfau_async_tagwait_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg,
|
|
int8_t value)
|
|
{
|
|
cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 64 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 8 for 64 bit access.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_add64(cvmx_fau_reg64_t reg, s64 value)
|
|
{
|
|
cvmx_write64_int64(__cvmx_hwfau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 32 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 4 for 32 bit access.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_add32(cvmx_fau_reg32_t reg, s32 value)
|
|
{
|
|
reg ^= SWIZZLE_32;
|
|
cvmx_write64_int32(__cvmx_hwfau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 16 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 2 for 16 bit access.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_add16(cvmx_fau_reg16_t reg, s16 value)
|
|
{
|
|
reg ^= SWIZZLE_16;
|
|
cvmx_write64_int16(__cvmx_hwfau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 8 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_add8(cvmx_fau_reg8_t reg, int8_t value)
|
|
{
|
|
reg ^= SWIZZLE_8;
|
|
cvmx_write64_int8(__cvmx_hwfau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 64 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 8 for 64 bit access.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_write64(cvmx_fau_reg64_t reg, s64 value)
|
|
{
|
|
cvmx_write64_int64(__cvmx_hwfau_store_address(1, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 32 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 4 for 32 bit access.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_write32(cvmx_fau_reg32_t reg, s32 value)
|
|
{
|
|
reg ^= SWIZZLE_32;
|
|
cvmx_write64_int32(__cvmx_hwfau_store_address(1, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 16 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 2 for 16 bit access.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_write16(cvmx_fau_reg16_t reg, s16 value)
|
|
{
|
|
reg ^= SWIZZLE_16;
|
|
cvmx_write64_int16(__cvmx_hwfau_store_address(1, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 8 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_hwfau_atomic_write8(cvmx_fau_reg8_t reg, int8_t value)
|
|
{
|
|
reg ^= SWIZZLE_8;
|
|
cvmx_write64_int8(__cvmx_hwfau_store_address(1, reg), value);
|
|
}
|
|
|
|
/** Allocates 64bit FAU register.
|
|
* @return value is the base address of allocated FAU register
|
|
*/
|
|
int cvmx_fau64_alloc(int reserve);
|
|
|
|
/** Allocates 32bit FAU register.
|
|
* @return value is the base address of allocated FAU register
|
|
*/
|
|
int cvmx_fau32_alloc(int reserve);
|
|
|
|
/** Allocates 16bit FAU register.
|
|
* @return value is the base address of allocated FAU register
|
|
*/
|
|
int cvmx_fau16_alloc(int reserve);
|
|
|
|
/** Allocates 8bit FAU register.
|
|
* @return value is the base address of allocated FAU register
|
|
*/
|
|
int cvmx_fau8_alloc(int reserve);
|
|
|
|
/** Frees the specified FAU register.
|
|
* @param address Base address of register to release.
|
|
* @return 0 on success; -1 on failure
|
|
*/
|
|
int cvmx_fau_free(int address);
|
|
|
|
/** Display the fau registers array
|
|
*/
|
|
void cvmx_fau_show(void);
|
|
|
|
#endif /* __CVMX_HWFAU_H__ */
|