156 lines
5.0 KiB
C
156 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2021 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2021 Rockchip, Inc.
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*
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* Copyright (C) 2018 Texas Instruments, Inc
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*/
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#ifndef PCIE_DW_COMMON_H
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#define PCIE_DW_COMMON_H
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#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
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/* PCI DBICS registers */
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#define PCIE_LINK_STATUS_REG 0x80
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#define PCIE_LINK_STATUS_SPEED_OFF 16
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#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
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#define PCIE_LINK_STATUS_WIDTH_OFF 20
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#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
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/*
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* iATU Unroll-specific register definitions
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* From 4.80 core version the address translation will be made by unroll.
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* The registers are offset from atu_base
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*/
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_UNR_LOWER_BASE 0x08
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#define PCIE_ATU_UNR_UPPER_BASE 0x0c
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#define PCIE_ATU_UNR_LIMIT 0x10
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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/* Register address builder */
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU_US 10000
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/* PCI DBICS registers */
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#define PCIE_LINK_STATUS_REG 0x80
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#define PCIE_LINK_STATUS_SPEED_OFF 16
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#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
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#define PCIE_LINK_STATUS_WIDTH_OFF 20
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#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
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#define PCIE_LINK_CAPABILITY 0x7c
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#define PCIE_LINK_CTL_2 0xa0
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#define TARGET_LINK_SPEED_MASK 0xf
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#define LINK_SPEED_GEN_1 0x1
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#define LINK_SPEED_GEN_2 0x2
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#define LINK_SPEED_GEN_3 0x3
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/* Synopsys-specific PCIe configuration registers */
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_DLL_LINK_EN BIT(5)
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#define PORT_LINK_FAST_LINK_MODE BIT(7)
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#define PORT_LINK_MODE_MASK GENMASK(21, 16)
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#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
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#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
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#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
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#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
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#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)
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#define PORT_LOGIC_SPEED_CHANGE BIT(17)
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#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
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#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
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#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
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#define PCIE_MISC_CONTROL_1_OFF 0x8bc
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#define PCIE_DBI_RO_WR_EN BIT(0)
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU 10000
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/**
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* struct pcie_dw - DW PCIe controller state
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*
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* @dbi_base: The base address of dbi register space
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* @cfg_base: The base address of configuration space
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* @atu_base: The base address of ATU space
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* @cfg_size: The size of the configuration space which is needed
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* as it gets written into the PCIE_ATU_LIMIT register
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* @first_busno: This driver supports multiple PCIe controllers.
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* first_busno stores the bus number of the PCIe root-port
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* number which may vary depending on the PCIe setup
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* (PEX switches etc).
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* @io: The IO space for EP's BAR
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* @mem: The memory space for EP's BAR
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* @prefetch: The prefetch space for EP's BAR
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*/
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struct pcie_dw {
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struct udevice *dev;
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void __iomem *dbi_base;
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void __iomem *cfg_base;
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void __iomem *atu_base;
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fdt_size_t cfg_size;
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int first_busno;
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/* IO, MEM & PREFETCH PCI regions */
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struct pci_region io;
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struct pci_region mem;
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struct pci_region prefetch;
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};
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int pcie_dw_get_link_speed(struct pcie_dw *pci);
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int pcie_dw_get_link_width(struct pcie_dw *pci);
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int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index, int type, u64 cpu_addr,
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u64 pci_addr, u32 size);
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int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep,
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enum pci_size_t size);
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int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value,
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enum pci_size_t size);
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static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en)
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{
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u32 val;
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val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
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if (en)
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val |= PCIE_DBI_RO_WR_EN;
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else
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val &= ~PCIE_DBI_RO_WR_EN;
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writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
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}
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void pcie_dw_setup_host(struct pcie_dw *pci);
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#endif
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