144 lines
3.0 KiB
C
144 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PRNG driver for Qualcomm IPQ40xx
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*
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* Copyright (c) 2020 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*
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* Based on Linux driver
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <rng.h>
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/* Device specific register offsets */
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#define PRNG_DATA_OUT 0x0000
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#define PRNG_STATUS 0x0004
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#define PRNG_LFSR_CFG 0x0100
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#define PRNG_CONFIG 0x0104
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/* Device specific register masks and config values */
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#define PRNG_LFSR_CFG_MASK 0x0000ffff
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#define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
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#define PRNG_CONFIG_HW_ENABLE BIT(1)
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#define PRNG_STATUS_DATA_AVAIL BIT(0)
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#define MAX_HW_FIFO_DEPTH 16
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#define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4)
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#define WORD_SZ 4
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struct msm_rng_priv {
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phys_addr_t base;
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struct clk clk;
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};
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static int msm_rng_read(struct udevice *dev, void *data, size_t len)
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{
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struct msm_rng_priv *priv = dev_get_priv(dev);
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size_t currsize = 0;
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u32 *retdata = data;
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size_t maxsize;
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u32 val;
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/* calculate max size bytes to transfer back to caller */
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maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
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/* read random data from hardware */
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do {
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val = readl_relaxed(priv->base + PRNG_STATUS);
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if (!(val & PRNG_STATUS_DATA_AVAIL))
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break;
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val = readl_relaxed(priv->base + PRNG_DATA_OUT);
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if (!val)
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break;
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*retdata++ = val;
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currsize += WORD_SZ;
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/* make sure we stay on 32bit boundary */
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if ((maxsize - currsize) < WORD_SZ)
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break;
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} while (currsize < maxsize);
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return 0;
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}
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static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
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{
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u32 val;
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if (enable) {
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/* Enable PRNG only if it is not already enabled */
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val = readl_relaxed(priv->base + PRNG_CONFIG);
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if (val & PRNG_CONFIG_HW_ENABLE) {
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val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
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val &= ~PRNG_LFSR_CFG_MASK;
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val |= PRNG_LFSR_CFG_CLOCKS;
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writel(val, priv->base + PRNG_LFSR_CFG);
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val = readl_relaxed(priv->base + PRNG_CONFIG);
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val |= PRNG_CONFIG_HW_ENABLE;
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writel(val, priv->base + PRNG_CONFIG);
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}
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} else {
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val = readl_relaxed(priv->base + PRNG_CONFIG);
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val &= ~PRNG_CONFIG_HW_ENABLE;
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writel(val, priv->base + PRNG_CONFIG);
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}
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return 0;
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}
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static int msm_rng_probe(struct udevice *dev)
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{
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struct msm_rng_priv *priv = dev_get_priv(dev);
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int ret;
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret < 0)
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return ret;
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return msm_rng_enable(priv, 1);
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}
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static int msm_rng_remove(struct udevice *dev)
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{
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struct msm_rng_priv *priv = dev_get_priv(dev);
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return msm_rng_enable(priv, 0);
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}
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static const struct dm_rng_ops msm_rng_ops = {
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.read = msm_rng_read,
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};
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static const struct udevice_id msm_rng_match[] = {
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{ .compatible = "qcom,prng", },
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{},
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};
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U_BOOT_DRIVER(msm_rng) = {
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.name = "msm-rng",
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.id = UCLASS_RNG,
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.of_match = msm_rng_match,
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.ops = &msm_rng_ops,
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.probe = msm_rng_probe,
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.remove = msm_rng_remove,
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.priv_auto = sizeof(struct msm_rng_priv),
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};
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